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* panfrost: Initial implementation of panfrost_job_submitRohan Garg2019-06-183-5/+23
| | | | | | | | Start fleshing out panfrost_job v2: [Alyssa: Remove unused variable, warning introduced] Reviewed-by: Alyssa Rosenzweig <[email protected]>
* virgl_hw: add YUV supportGurchetan Singh2019-06-181-0/+6
| | | | | | Add corresponding entries from p_format.h Reviewed-by: Emil Velikov <[email protected]>
* virgl: sync to virglrenderer virgl_hw.hGurchetan Singh2019-06-181-3/+10
| | | | | | | It's nice to keep these two files in sync, as they define guest userspace <---> host userspace communcation. Reviewed-by: Emil Velikov <[email protected]>
* anv: Make border colors the right size and alignment on HSWJason Ekstrand2019-06-182-12/+48
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* imgui: bump imgui memory editor copyLionel Landwerlin2019-06-182-30/+38
| | | | | | | | | | | | Getting rid of a compiler warning : In file included from ../src/intel/tools/aubinator_viewer.cpp:225: ../src/imgui/imgui_memory_editor.h: In member function ‘void MemoryEditor::DisplayPreviewData(size_t, const u8*, size_t, MemoryEditor::DataType, MemoryEditor::DataFormat, char*, size_t) const’: ../src/imgui/imgui_memory_editor.h:637:16: warning: enumeration value ‘DataType_COUNT’ not handled in switch [-Wswitch] switch (data_type) ^ Signed-off-by: Lionel Landwerlin <[email protected]>
* panfrost/midgard: Enable autovectorizationAlyssa Rosenzweig2019-06-181-2/+1
| | | | | | Enable nir_opt_vectorize. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* nir: add a vectorization passConnor Abbott2019-06-184-0/+457
| | | | | | | | | | | | | | | | | | | | | | | | | | This effectively does the opposite of nir_lower_alus_to_scalar, trying to combine per-component ALU operations with the same sources but different swizzles into one larger ALU operation. It uses a similar model as CSE, where we do a depth-first approach and keep around a hash set of instructions to be combined, but there are a few major differences: 1. For now, we only support entirely per-component ALU operations. 2. Since it's not always guaranteed that we'll be able to combine equivalent instructions, we keep a stack of equivalent instructions around, trying to combine new instructions with instructions on the stack. The pass isn't comprehensive by far; it can't handle operations where some of the sources are per-component and others aren't, and it can't handle phi nodes. But it should handle the more common cases, and it should be reasonably efficient. [Alyssa: Rebase on latest master, updating with respect to typeless moves] Acked-by: Alyssa Rosenzweig <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* panfrost: Add support for TXS instructionsBoris Brezillon2019-06-183-2/+60
| | | | | | | | | | | | | This patch adds support for nir_texop_txs instructions which are needed to support the OpenGL textureSize() function. This is also needed to support RECT texture sampling which is currently lowered to 2D sampling + a TXS() instruction by the nir_lower_tex() helper. Changes in v2: * Split options for the 1st and 2nd tex lowering passes Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Prepare things to support non-native texture opsBoris Brezillon2019-06-181-16/+19
| | | | | | | | | We are about to add support for the TXS (texture size) op which is not implemented using a midgard texture instruction. Let's rename emit_tex() into emit_texop_native() and repurpose emit_tex() as a dispatcher. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Move sysval upload logic out of panfrost_emit_for_draw()Boris Brezillon2019-06-182-17/+54
| | | | | | | | | | | | We're about to add more sysval types, and panfrost_emit_for_draw() is big enough, so let's move the sysval upload logic in a separate function. We also add one sub-function per sysval type to keep the panfrost_upload_sysvals() small/readable. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Make the sysval logic more genericBoris Brezillon2019-06-181-22/+39
| | | | | | | | | | | We are about to add support for nir_texop_txs which requires adding a sysval/uniform containing the texture size. Let's change the emit_sysval_read() prototype to take a nir_instr object instead of a nir_intrinsic_instr one so we can re-use this function when emitting a sysval for a txs instruction. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* nir/lower_tex: Add a way to lower TXS(non-0-LOD) instructionsBoris Brezillon2019-06-182-0/+52
| | | | | | | | | | | | | | | The V3D driver has an open-coded solution for this, and we need the same thing for Panfrost, so let's add a generic way to lower TXS(LOD) into max(TXS(0) >> LOD, 1). Changes in v2: * Use == 0 instead of ! * Rework the minification logic as suggested by Jason * Assign cursor pos at the beginning of the function * Patch the LOD just after retrieving the old value Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* nir/lower_tex: Update ->sampler_dim value before calling get_texture_size()Boris Brezillon2019-06-181-2/+5
| | | | | | | | | | | | | | | | | | | | | | get_texture_size() will create a txs instruction with ->sampler_dim set to the original tex->sampler_dim. The condition to call lower_rect() only checks the value of ->sampler_dim and whether lower_rect is requested or not. This leads to an infinite loop when calling nir_lower_tex() with the same options until it returns false. In order to avoid that, let's move the tex->sampler_dim patching before get_texture_size() is called. This way the txs instruction will have ->sampler_dim set to GLSL_SAMPLER_DIM_2D and nir_lower_tex() won't try to lower it on the subsequent passes. Changes in v2: * Add Jason R-b * Add a comment explaining why we patch ->sampler_dim at the beginning of the lower_rect() func Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* nir/lower_tex: Actually report when projector lowering happenedBoris Brezillon2019-06-181-4/+4
| | | | | | | | | | | | | | | | | The code considers that projector lowering was done even if it's not really the case. Change the project_src() prototype to return a bool encoding whether projector lowering happened or not and update the progress var accordingly in nir_lower_tex_block(). --- Changes in v2: * Add Jason R-b * Drop the part suggesting that nir_lower_rect() could be called in a do-while(progress) loop. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Adapt to constant name change in UABITomeu Vizoso2019-06-182-3/+5
| | | | | | | We hadn't updated the kernel header after the driver got into mainline. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: ci: Update resultsTomeu Vizoso2019-06-181-15/+0
| | | | | | | Alyssa fixed some failing tests last night. Signed-off-by: Tomeu Vizoso <[email protected]> Acked-by: Alyssa Rosenzweig <[email protected]>
* radv: adjust the DCC base VA for mipmapped color attachmentsSamuel Pitoiset2019-06-181-0/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix color decompressions for FMASK/CMASKSamuel Pitoiset2019-06-181-1/+2
| | | | | | | | Only skip levels without DCC when it's a DCC decompression. Whoops. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not decompress levels without DCC with the graphics pathSamuel Pitoiset2019-06-181-15/+20
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not decompress levels without DCC with the compute pathSamuel Pitoiset2019-06-181-0/+5
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: check if DCC is enabled per mip not for the whole imageSamuel Pitoiset2019-06-186-19/+23
| | | | | | | | In other words, make use of radv_dcc_enabled() instead of radv_image_has_dcc() all over the places. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* v3d: implement simultaneous peripheral access exceptions for V3D 4.1+Iago Toral Quiroga2019-06-183-6/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Shader-db results: total instructions in shared programs: 9117550 -> 9102719 (-0.16%) instructions in affected programs: 1752873 -> 1738042 (-0.85%) helped: 7076 HURT: 478 helped stats (abs) min: 1 max: 22 x̄: 2.19 x̃: 2 helped stats (rel) min: 0.07% max: 13.89% x̄: 1.70% x̃: 1.07% HURT stats (abs) min: 1 max: 7 x̄: 1.41 x̃: 1 HURT stats (rel) min: 0.09% max: 10.17% x̄: 0.86% x̃: 0.54% 95% mean confidence interval for instructions value: -2.00 -1.92 95% mean confidence interval for instructions %-change: -1.58% -1.50% Instructions are helped. total max-temps in shared programs: 1327774 -> 1327728 (<.01%) max-temps in affected programs: 1025 -> 979 (-4.49%) helped: 47 HURT: 2 helped stats (abs) min: 1 max: 2 x̄: 1.02 x̃: 1 helped stats (rel) min: 2.63% max: 20.00% x̄: 7.67% x̃: 5.26% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 4.17% max: 4.17% x̄: 4.17% x̃: 4.17% 95% mean confidence interval for max-temps value: -1.06 -0.82 95% mean confidence interval for max-temps %-change: -8.89% -5.49% Max-temps are helped. Reviewed-by: Eric Anholt <[email protected]>
* v3d: only flush jobs accessing the query BO when reading query resultsIago Toral Quiroga2019-06-181-2/+2
| | | | Reviewed-by: Eric Anholt <[email protected]>
* v3d: add a helper function to flush jobs using a BOIago Toral Quiroga2019-06-182-0/+12
| | | | | | v2: use _mesa_set_search() (Eric) Reviewed-by: Eric Anholt <[email protected]>
* iris: Support more RGBX pipe formats.Kenneth Graunke2019-06-171-2/+13
| | | | | | | | Without them, the state tracker falls back to an RGBA format, but it doesn't always manage to override the swizzle for us. So we lose the information that the API expects an X channel, where alpha is garbage and reads back as 1. We have no equivalent ISL RGBX format for these, so we just use RGBA directly and override the swizzle in all cases.
* glsl: Fix out of bounds read in shader_cache_read_program_metadataKenneth Graunke2019-06-171-3/+2
| | | | | | | | | | | | | | | | | | The VaryingNames array has NumVaryings entries. But BufferStride is a small array of MAX_FEEDBACK_BUFFERS (4) entries. Programs with more than 4 varyings would read out of bounds. Also, BufferStride is set based on the shader itself, which means that it's inherently already included in the hash, and doesn't need to be included again. At the point when shader_cache_read_program_metadata is called, the linker hasn't even set those fields yet. So, just drop it entirely. Fixes valgrind errors in KHR-GL45.transform_feedback.linking_errors_test. Fixes: 6d830940f78 glsl/shader_cache: Allow shader cache usage with transform feedback Reviewed-by: Timothy Arceri <[email protected]>
* anv: Set STATE_BASE_ADDRESS upper bounds on gen7Jason Ekstrand2019-06-171-0/+17
| | | | | | | | | This should fix floating-point border color on all gen7 HW. Integer is still thoroughly busted on gen7 because it doesn't exist on IVB and it's crazy on HSW. Cc: [email protected] Reviewed-by: Kenneth Graunke <[email protected]>
* radv: Disable linear tiled compressed textures.Bas Nieuwenhuizen2019-06-181-0/+4
| | | | | | Support got removed in the new addrlib update. Reviewed-by: Samuel Pitoiset <[email protected]>
* anv:Use VK_EXT_separate_stencil_usage to avoid stencil shadows on gen7Jason Ekstrand2019-06-174-2/+16
| | | | | | | | | | Whenever stencil texturing is not required (most of the time), we can use VK_EXT_separate_stencil_usage to only create the shadow image when VK_IMAGE_USAGE_SAMPLED_BIT is required for stencil. Of course, this depends on applications to use the extension but hopefully DXVK and similar translators are doing so and that covers most of the apps. Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: Add stencil texturing support for gen7Jason Ekstrand2019-06-173-7/+96
| | | | | | | | | | | | Intel hardware didn't get support for sampling from W-tiled (required for stencil) images until Broadwell so we can't directly sample from stencil. Instead, if we want to support stencil texturing on gen7 hardware, we have to keep a texture-capable shadow copy around and use BLORP to update when stencil changes. The one thing this commit does not implement is self-dependencies with stencil input attachments. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99493 Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/blorp: Update shadow images when clearing or uploadingJason Ekstrand2019-06-171-11/+104
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/cmd_buffer: Add a stencil transition helperJason Ekstrand2019-06-171-35/+75
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/blorp: Take an aspect in anv_image_copy_to_shadowJason Ekstrand2019-06-173-3/+4
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* anv/formats: Re-arrange the way se set some flag bitsJason Ekstrand2019-06-171-6/+5
| | | | Reviewed-by: Lionel Landwerlin <[email protected]>
* iris: Make resource_copy_region handle packed depth-stencil resources.Kenneth Graunke2019-06-171-0/+10
| | | | | | Also copy along the separate stencil buffer if needed. Fixes Piglit's arb_copy_image-formats.
* iris: Order CS stall and TC invalidate for format reinterpretation hacksKenneth Graunke2019-06-171-3/+2
| | | | | | | | This should ensure the TC invalidate happens after the stall. Fixes KHR-GL43.copy_image.functional which does a CopyImage (blorp_copy) from a buffer (using R8G8B8A8_UINT), then GetTexImage to read back the original image (using R10G10B10A2_UNORM).
* iris: Be more aggressive at post-format-reintepret TC invalidate hackKenneth Graunke2019-06-171-8/+5
| | | | | | | | | | | | | | When copying/blitting with format reinterpretation, we invalidate the texture cache before/after. Before is so the source of the copy works, and after is to get rid of our new data in the "wrong" format to protect future attempts to sample. When I ported these hacks to iris, I tried to be cautious by only bothering with the hacks if the batch referenced the BO. This makes some sense for the before case. If it isn't referenced, the texture cache can't really have any data for the BO (since it's also invalidated between batches). But we still need to do the after case regardless, as we've just polluted the cache with hazardous entries.
* virgl: Assume sRGB write control for older guest kernels or virglrenderer hostsGert Wollny2019-06-171-1/+2
| | | | | | | | | | | | | | | | When the host virglrenderer is an older version that doesn't check the sRGB write control feature, or when the guest kernel doesn't support CAPS v2, then the guest will only report support for GL 2.1 on a GL 3.3 host, even though it was supporting 3.3 with earlier guest mesa versions. By also checking the host feature check version this regression can be avoided. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110921 Fixes: 2845939d6a72 virgl: Set sRGB write control CAP based on host capabilities Signed-off-by: Gert Wollny <[email protected]> Reviewed-by: Chia-I Wu <[email protected]>
* freedreno/a6xx: disallow UBWC for x24s8Rob Clark2019-06-171-4/+15
| | | | | | | | | Fixes: dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d dEQP-GLES31.functional.stencil_texturing.misc.compare_mode_effect Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: un-swap X24S8_UINTRob Clark2019-06-172-5/+6
| | | | | | | | | | | | | | | | | | | The stencil is actually in the .w component, but we used to use SWAP to remap the channels. This doesn't work when tiled/ubwc. Fixes: dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_2d_array dEQP-GLES31.functional.stencil_texturing.format.depth24_stencil8_cube dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_2d_array dEQP-GLES31.functional.stencil_texturing.format.stencil_index8_cube dEQP-GLES31.functional.stencil_texturing.misc.base_level dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_pot dEQP-GLES31.functional.texture.border_clamp.formats.stencil_index8.nearest_size_npot dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_pot dEQP-GLES31.functional.texture.border_clamp.formats.depth24_stencil8_sample_stencil.nearest_size_npot dEQP-GLES31.functional.texture.border_clamp.sampler.uint_stencil Signed-off-by: Rob Clark <[email protected]>
* radv: add mipmaps support for DCC decompression on computeSamuel Pitoiset2019-06-171-52/+54
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add mipmaps support for color decompressions (DCC/FMASK/CMASK)Samuel Pitoiset2019-06-171-99/+129
| | | | | | | And some cleanups. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: set the DCC/FCE predicates from the base levelSamuel Pitoiset2019-06-171-0/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: load the fast color clear values from the base levelSamuel Pitoiset2019-06-171-6/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store the DCC predicate for each mipSamuel Pitoiset2019-06-176-26/+72
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store the FCE predicate for each mipSamuel Pitoiset2019-06-174-10/+32
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: store the fast color clear values for each mipSamuel Pitoiset2019-06-173-13/+39
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: allocate DCC metadata for each mipSamuel Pitoiset2019-06-171-4/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* gallium: Remove unused util_ringbufferCaio Marcelo de Oliveira Filho2019-06-174-193/+0
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* llvmpipe: Don't use u_ringbuffer for lp_scene_queueCaio Marcelo de Oliveira Filho2019-06-171-36/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Inline the ring buffer and signal logic into lp_scene_queue instead of using a u_ringbuffer. The code ends up simpler since there's no need to handle serializing data from / to packets. This fixes a crash when compiling Mesa with LTO, that happened because of util_ringbuffer_dequeue() was writing data after the "header packet", as shown below struct scene_packet { struct util_packet header; struct lp_scene *scene; }; /* Snippet of old lp_scene_deque(). */ packet.scene = NULL; ret = util_ringbuffer_dequeue(queue->ring, &packet.header, sizeof packet / 4, return packet.scene; but due to the way aliasing analysis work the compiler didn't considered the "&packet->header" to alias with "packet->scene". With the aggressive inlining done by LTO, this would end up always returning NULL instead of the content read by util_ringbuffer_dequeue(). Issue found by Marco Simental and iThiago Macieira. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110884 Reviewed-by: Roland Scheidegger <[email protected]>
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