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* i965/vec4: use vec4_builder to emit instructions in setup_imm_df()Samuel Iglesias Gonsálvez2017-04-142-50/+50
* i965/vec4: consider subregister offset in live variablesJuan A. Suarez Romero2017-04-141-2/+2
* i965/vec4: fix assert to detect SIMD lowered DF instructions in IVBFrancisco Jerez2017-04-141-5/+1
* i965/vec4: split VEC4_OPCODE_FROM_DOUBLE into one opcode per destination's typeSamuel Iglesias Gonsálvez2017-04-147-27/+60
* i965/vec4: split d2x conversion and data gathering from one opcode to two exp...Samuel Iglesias Gonsálvez2017-04-142-8/+1
* i965/vec4: fix VEC4_OPCODE_FROM_DOUBLE for IVB/BYTJuan A. Suarez Romero2017-04-141-7/+19
* i965/vec4: keep original type when dealing with null registersJuan A. Suarez Romero2017-04-141-0/+2
* i965/vec4: split DF instructions and later double its execsize in IVB/BYTSamuel Iglesias Gonsálvez2017-04-143-1/+53
* i965/fs: lower all non-force_writemask_all DF instructions to SIMD4 on IVB/BYTSamuel Iglesias Gonsálvez2017-04-141-0/+9
* i965/fs: Get 64-bit indirect moves working on IVB.Francisco Jerez2017-04-141-2/+25
* i965: Use source region <1,2,0> when converting to DF.Matt Turner2017-04-142-13/+28
* i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECTJuan A. Suarez Romero2017-04-141-3/+14
* i965/fs: fix dst stride in IVB/BYT type conversionsJuan A. Suarez Romero2017-04-141-27/+41
* i965/fs: rename lower_d2x to lower_conversionsSamuel Iglesias Gonsálvez2017-04-144-4/+4
* Revert "i965/fs: Don't emit SEL instructions for type-converting MOVs."Samuel Iglesias Gonsálvez2017-04-141-2/+0
* i965/fs: generalize the legalization d2x passSamuel Iglesias Gonsálvez2017-04-142-37/+67
* i965: Use <0,2,1> region for scalar DF sources on IVB/BYT.Matt Turner2017-04-141-0/+13
* i965/fs: clamp exec_size when an instruction has a scalar DF sourceSamuel Iglesias Gonsálvez2017-04-141-3/+8
* i965/fs: double regioning parameters and execsize for DF in IVB/BYTJuan A. Suarez Romero2017-04-141-7/+43
* i965/fs: add helper to retrieve instruction execution typeJuan A. Suarez Romero2017-04-143-5/+64
* i965: Handle IVB DF differences in the validator.Matt Turner2017-04-141-0/+24
* i965/disasm: also print nibctrl in IVB for execsize=8Iago Toral Quiroga2017-04-141-3/+3
* nir: Destination component count of shader_clock intrinsic is 2Boyan Ding2017-04-142-2/+3
* radeonsi: add missing initialization for userptr buffersNicolai Hähnle2017-04-141-0/+4
* radv: remove the temp descriptor set infrastructureFredrik Höglund2017-04-142-76/+28
* radv: use push descriptors in metaFredrik Höglund2017-04-146-416/+301
* radv: add private push descriptors for metaFredrik Höglund2017-04-142-0/+41
* anv/blorp: Properly handle VK_ATTACHMENT_UNUSEDJason Ekstrand2017-04-141-5/+22
* anv/cmd_buffer: Use the null surface state for ATTACHMENT_UNUSEDJason Ekstrand2017-04-141-2/+14
* anv/cmd_buffer: Always set up a null surface stateJason Ekstrand2017-04-141-31/+19
* radeonsi: cope with missing disassemblyNicolai Hähnle2017-04-141-1/+2
* gallium/ddebug: dump missing members of pipe_draw_infoNicolai Hähnle2017-04-142-0/+7
* radeonsi: enable ARB_shader_viewport_layer_arrayNicolai Hähnle2017-04-143-2/+3
* radeonsi: handle ignored LAYER and VIEWPORT_INDEX writesNicolai Hähnle2017-04-141-0/+20
* st/mesa: enable ARB_shader_viewport_layer_arrayNicolai Hähnle2017-04-141-0/+5
* tgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX}Nicolai Hähnle2017-04-141-0/+10
* gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORTNicolai Hähnle2017-04-1417-0/+19
* configure.ac: add --enable-sanitize optionNicolai Hähnle2017-04-141-1/+27
* anv/cmd_buffer: Flush the VF cache at the top of all primariesJason Ekstrand2017-04-141-0/+12
* anv/blorp: Flush the texture cache in UpdateBufferJason Ekstrand2017-04-141-0/+7
* anv: Limit VkDeviceMemory objects to 2GBJason Ekstrand2017-04-141-0/+20
* intel/blorp: Add a blorp_emit_dynamic macroJason Ekstrand2017-04-141-64/+50
* swr: Enable MSAA in OpenSWR software rendererBruce Cherniak2017-04-146-25/+313
* swr: Removed unnecessary PIPE_BIND flags from swr_is_format_supportedBruce Cherniak2017-04-141-2/+1
* swr: Align swr_context allocation to SIMD alignment.Bruce Cherniak2017-04-141-2/+5
* swr: update gallium driver docsTim Rowley2017-04-142-6/+12
* radv: remove irrelevant commentGrazvydas Ignotas2017-04-141-1/+1
* radv: report timestampPeriod correctlyGrazvydas Ignotas2017-04-142-2/+2
* nir/print: add compute shader infoRob Clark2017-04-141-0/+13
* gallium/docs: small correction about register files for atomicsRob Clark2017-04-141-2/+4
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