summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* winsys/amdgpu: update amdgpu_addr_create for GFX9Marek Olšák2017-03-301-17/+29
* winsys/amdgpu: rename GFX6 surface functionsMarek Olšák2017-03-301-25/+29
* gallium/radeon: add GFX9 surface info to radeon_surfMarek Olšák2017-03-301-0/+38
* gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*Marek Olšák2017-03-3020-345/+357
* radeonsi/gfx9: allow Z16_UNORM for TC-compatible HTILEMarek Olšák2017-03-301-6/+16
* radeonsi/gfx9: draw changesMarek Olšák2017-03-301-12/+31
* radeonsi/gfx9: pad shader binaries by 128 bytesMarek Olšák2017-03-301-0/+6
* radeonsi/gfx9: trivial shader and ring changesMarek Olšák2017-03-301-5/+15
* radeonsi/gfx9: sampler state changesMarek Olšák2017-03-301-1/+1
* radeonsi/gfx9: add a scissor bug workaroundMarek Olšák2017-03-301-0/+6
* radeonsi/gfx9: rasterizer changesMarek Olšák2017-03-301-2/+4
* radeonsi/gfx9: disable the 2-bit format fetch fixMarek Olšák2017-03-301-2/+6
* radeonsi/gfx9: set NUM_RECORDS correctlyMarek Olšák2017-03-303-3/+3
* radeonsi/gfx9: ELEMENT_SIZE changeMarek Olšák2017-03-302-7/+15
* radeonsi/gfx9: enable ETC2Marek Olšák2017-03-301-1/+2
* radeonsi/gfx9: disable RB+ on Vega10Marek Olšák2017-03-306-22/+39
* radeonsi/gfx9: init_config changesMarek Olšák2017-03-302-6/+36
* radeonsi/gfx9: don't set PA_SC_RASTER_CONFIG*Marek Olšák2017-03-301-15/+19
* radeonsi/gfx9: Gather4 no longer needs the workaroundMarek Olšák2017-03-301-1/+2
* radeonsi/gfx9: CP DMA changesMarek Olšák2017-03-302-10/+31
* radeonsi/gfx9: query changes - EVENT_WRITE and SET_PREDICATIONMarek Olšák2017-03-301-10/+19
* radeonsi/gfx9: EVENT_WRITE_EOP -> RELEASE_MEMMarek Olšák2017-03-301-14/+25
* radeonsi/gfx9: INDIRECT_BUFFER changeMarek Olšák2017-03-301-1/+1
* radeonsi/gfx9: enable SDMA buffer copying & clearingMarek Olšák2017-03-301-3/+4
* radeonsi/gfx9: handle GFX9 in a few placesMarek Olšák2017-03-304-2/+5
* radeonsi/gfx9: don't read back non-existent SRBM registersMarek Olšák2017-03-301-3/+5
* radeonsi/gfx9: add IB parser supportMarek Olšák2017-03-304-19/+37
* radeonsi/gfx9: set the LLVM processor, require LLVM 5.0Marek Olšák2017-03-302-0/+9
* radeonsi/gfx9: add GFX9 and VEGA10 enumsMarek Olšák2017-03-304-5/+15
* amd: GFX9 packet changesMarek Olšák2017-03-304-13/+26
* amd: define event types for GFX9Marek Olšák2017-03-301-0/+54
* amd: add texture format definitions for GFX9Marek Olšák2017-03-305-27/+152
* amd: resolve remaining definition conflicts with gfx9d.hMarek Olšák2017-03-305-66/+66
* amd: normalize register definition formattingMarek Olšák2017-03-303-92/+174
* amd: import GFX9 register definitionsMarek Olšák2017-03-302-0/+7287
* radeonsi: code shuffling in si_init_depth_surfaceMarek Olšák2017-03-301-54/+32
* amd/addrlib: silence warningsMarek Olšák2017-03-304-15/+15
* amd/addrlib: import gfx9 supportNicolai Hähnle2017-03-3019-3/+22053
* amd/addrlib: Not all ETC2 formats are 128bpp... add new ETC2 formats to diffe...Kevin Furrow2017-03-303-19/+45
* amd/addrlib: Fix selection of swizzle modes for 3D compressed images.Kevin Furrow2017-03-301-1/+2
* amd/addrlib: Add support for ETC2 and ASTC formats.Kevin Furrow2017-03-303-1/+119
* amd/addrlib: Bump version to 6.02Joe Ma2017-03-301-1/+1
* amd/addrlib: Adjust slie size after pitch and actual height adjustmentFrans Gu2017-03-301-26/+31
* amd/addrlib: Apply input pitch after internal pitch aligningFrans Gu2017-03-301-12/+33
* amdgpu/addrlib: Bump version to 6.01Nicolai Hähnle2017-03-301-2/+2
* amdgpu/addrlib: Seperate 2 dcc related workarounds by different flagsNicolai Hähnle2017-03-303-3/+9
* amdgpu/addrlib: Fix the issue that tcCompatible HTILE slice size is not calcu...Nicolai Hähnle2017-03-302-0/+18
* amdgpu/addrlib: Add a new output flag to notify client that the returned tile...Nicolai Hähnle2017-03-302-1/+5
* amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixesXavi Zhang2017-03-304-20/+152
* amdgpu/addrlib: Adjust bank equation bit order based on macro tile aspect rat...Frans Gu2017-03-304-91/+282
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-23 10:50:10 +0000