summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* radv: fix memory leaks in radv_load_meta_pipeline()Samuel Pitoiset2018-08-151-2/+3
| | | | | | | | Reported by Coverity. Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: drop wrong initialization of COMPUTE_RESOURCE_LIMITSSamuel Pitoiset2018-08-151-3/+1
| | | | | | | | | | | | The last parameter of radeon_set_sh_reg_seq() is the number of dwords to emit. We were lucky because WAVES_PER_SH(0x3) is 3 but it was initialized to 0. COMPUTE_RESOURCE_LIMITS is correctly set when generating compute pipelines, so we don't need to initialize it. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* docs: update calendar 18.2.0-rc3 is outAndres Gomez2018-08-151-8/+2
| | | | Signed-off-by: Andres Gomez <[email protected]>
* radv/meta_decompress: fix pointer to integer conversionMauro Rossi2018-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | VK_NULL_HANDLE replaces NULL to avoid following building error: external/mesa/src/amd/vulkan/radv_meta_decompress.c:365:54: error: incompatible pointer to integer conversion passing 'void *' to parameter of type 'VkShaderModule' (aka 'unsigned long long') [-Werror,-Wint-conversion] VkResult ret = create_pipeline(cmd_buffer->device, NULL, samples, ^~~~ prebuilts/clang/host/linux-x86/clang-4053586/lib64/clang/5.0.300080/include/stddef.h:105:16: note: expanded from macro 'NULL' # define NULL ((void*)0) ^~~~~~~~~~ external/mesa/src/amd/vulkan/radv_meta_decompress.c:97:32: note: passing argument to parameter 'vs_module_h' here VkShaderModule vs_module_h, ^ 1 error generated. Fixes: fbcd167314 ("radv: Add on-demand compilation of built-in shaders.") Signed-off-by: Mauro Rossi <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* egl/android: fix regression in drm_gralloc path (v2)Mauro Rossi2018-08-151-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a regression in mesa 18.2 and mesa-dev branches for HAVE_DRM_GRALLOC code path which is causing black screen on Android and prevents boot due to SIGSEGV MAPERR crash related to unproper handling of drm_gralloc drm FD in new droid_open_device() path. Problem is due to c7bb82136b ("egl/android: Add DRM node probing and filtering") To avoid the crash the former existing working droid_open_device() is restored, renamed droid_open_device_drm_gralloc() and kept within HAVE_DRM_GRALLOC braces. Tested with mesa-dev and mesa 18.2 branch and oreo-x86 bootanimation and Androdi GUI booting is fixed with i965, nouveau, radeon. The changes are compatible with gbm_gralloc, I've tested build with hwc too. (v2) remove indentation from HAVE_DRM_GRALLOC pre-processor directive NOTE: Definition of enum{} for GRALLOC_MODULE_PERFORM_GET_DRM_FD is not necessary and it's actually causing a redefinition building error, because in HAVE_DRM_GRALLOC path gralloc_drm.h is already exported by libgralloc_drm which is currently still a dependency. Fixes: c7bb82136b ("egl/android: Add DRM node probing and filtering") Cc: "18.2" <[email protected]> Signed-off-by: Mauro Rossi <[email protected]>
* mesa: shader dump/read support for ARB programsTapani Pälli2018-08-153-7/+31
| | | | | | Signed-off-by: Tapani Pälli <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106283 Reviewed-by: Alejandro Piñeiro <[email protected]>
* glsl: Avoid calling get_array_element for scalar constantsDanylo Piliaiev2018-08-151-1/+1
| | | | | | | | | | | | | Accessing scalar constant as an array in function call or initializer list triggered assert in get_array_element. Examples: func(0[0]); vec2 t = { 0[0], 0 }; Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107550 Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* radeonsi: enable 1 missing PS_SU perf counter on PolarisMarek Olšák2018-08-141-1/+1
|
* radeonsi: use radeon_info::nameMarek Olšák2018-08-143-40/+12
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* ac: add radeon_info::nameMarek Olšák2018-08-143-2/+12
| | | | Reviewed-by: Timothy Arceri <[email protected]>
* radeonsi: split si_clear_buffer to remove enum si_methodMarek Olšák2018-08-146-53/+60
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: replace CP_DMA_USE_L2 with enum si_cache_policyMarek Olšák2018-08-142-26/+41
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: declare coher in si_copy_bufferMarek Olšák2018-08-141-8/+7
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: make PFP_SYNC_ME an explicit CP DMA flagMarek Olšák2018-08-141-17/+25
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use emit_data->args in load_emitMarek Olšák2018-08-141-94/+37
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use emit_data->args in store_emitMarek Olšák2018-08-141-92/+71
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use emit_data->args in atomic_emitMarek Olšák2018-08-143-36/+47
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use emit_data->args in build_interp_intrinsicMarek Olšák2018-08-141-19/+13
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline atomic_fetch_argsMarek Olšák2018-08-141-74/+51
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline store_fetch_argsMarek Olšák2018-08-141-61/+42
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline load_fetch_argsMarek Olšák2018-08-141-39/+28
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: merge txq_emit and resq_emitMarek Olšák2018-08-141-48/+45
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline resq_fetch_argsMarek Olšák2018-08-141-62/+34
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline txq_fetch_argsMarek Olšák2018-08-141-26/+7
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: use get_resinfo directly in lower_gather4_integerMarek Olšák2018-08-141-13/+12
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: inline tex_fetch_args into build_tex_intrinsicMarek Olšák2018-08-141-222/+188
| | | | | | | The diff looks like it moves code that I didn't touch. Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: remove fetch_args callbacks for ALU instructionsMarek Olšák2018-08-142-103/+55
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: move internal TGSI shaders into si_shaderlib_tgsi.cMarek Olšák2018-08-148-319/+348
| | | | | Tested-by: Dieter Nützel <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: implement EXT_window_rectanglesMarek Olšák2018-08-149-2/+112
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/u_blitter: save/restore window rectanglesMarek Olšák2018-08-142-0/+29
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* noop: implement set_window_rectanglesMarek Olšák2018-08-141-0/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ddebug: implement set_window_rectanglesMarek Olšák2018-08-141-0/+12
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Add a new CFL PCI ID.Rodrigo Vivi2018-08-141-0/+1
| | | | | | | | | | | | One more CFL ID added to spec. Align with kernel commit d0e062ebb3a4 ("drm/i915/cfl: Add a new CFL PCI ID.") Cc: José Roberto de Souza <[email protected]> Cc: Anuj Phogat <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* freedreno/ir3: add support for a6xx 'merged' register setRob Clark2018-08-142-2/+24
| | | | | | | | | | Starting with a6xx, half and full precision registers conflict. Which makes things a bit more efficient, ie. if some parts of the shader are heavy on half-precision and others on full precision, you don't have to allocate the worst case for both. But it means we need to setup some additional conflicts. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: small RA cleanupRob Clark2018-08-142-13/+8
| | | | | | | Collapse is_temp() into it's only callsite, and pass compiler object as struct rather than void. Just cleanups to reduce noise in next patch. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: stop hard-coding FS input regsRob Clark2018-08-147-183/+103
| | | | | | | | | | We originally did this because at the time we didn't know all the bitfields to configure where various frag shader sysval's went. But we do. So switch to using sysvals for all the frag shader inputs. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use r63.x for unused inputsRob Clark2018-08-141-3/+3
| | | | | | | This way, unused sysval inputs, like frag_vcoord, get the correct regid value to disable the input. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: create all inputs in first blockRob Clark2018-08-141-17/+17
| | | | | | | | create_input()/create_input_compmask() should take the ctx as arg, rather than block, to enforce that all inputs are created in the first block, so that RA sees them as live at the start of the shader. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: rename s/frag_pos/frag_vcoord/gRob Clark2018-08-142-17/+22
| | | | | | | Make it more clear that this is varying fetch related. Also fixup some comments. Just cleanup for next patches. Signed-off-by: Rob Clark <[email protected]>
* compiler: add SYSTEM_VALUE_VARYING_COORDRob Clark2018-08-143-0/+8
| | | | | | | | Used internally in freedreno/ir3 for the vec2 value that hw passes to shader to use as coordinate for bary.f (varying fetch) instruction. This is not the same as SYSTEM_VALUE_FRAG_COORD. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move per-generation compiler configRob Clark2018-08-143-43/+52
| | | | | | | Move it from the compile ctx to the compiler object, before adding new things for a6xx. Signed-off-by: Rob Clark <[email protected]>
* radv: Update to new VK_EXT_vertex_attribute_divisor to version 2.Bas Nieuwenhuizen2018-08-142-4/+5
| | | | | | | | | | | | | Behavior wrt firstInstance got changed, and a divisor of 0 has been disallowed. The new version of the ext got published in specification 1.1.81. Sending to stable since the only known user is DXVK, which needs this for correctness. Reviewed-by: Samuel Pitoiset <[email protected]> CC: 18.2 <[email protected]>
* radv: Allow ETC2 on RAVEN and VEGA10 instead of all GFX9.Bas Nieuwenhuizen2018-08-141-1/+2
| | | | | | | Follow radeonsi. Fixes: 3665f66ef26 "radv: Add support for ETC2 textures." Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Fix missing Android platform define.Bas Nieuwenhuizen2018-08-142-1/+3
| | | | | CC: <[email protected]> Acked-by: Samuel Pitoiset <[email protected]>
* freedreno: move free() into fdN_context_destroy()Rob Clark2018-08-145-2/+7
| | | | | | | | Following patches will be doing further cleanup after calling fd_context_destroy() so it is easier if we move the free() into the per-gen backend code. Signed-off-by: Rob Clark <[email protected]>
* freedreno: a2xx: ir2 updateJonathan Marek2018-08-145-545/+615
| | | | | | | | | | | | | | | | | | | this patch brings a number of changes to ir2: -ir2 now generates CF clauses as necessary during assembly. this simplifies fd2_program/fd2_compiler and is necessary to implement optimization passes -ir2 now has separate vector/scalar instructions. this will make it easier to implementing scheduling of scalar+vector instructions together. dst_reg is also now seperate from src registers instead of a single list -ir2 now implements register allocation. this makes it possible to compile shaders which have more than 64 TGSI registers -ir2 now implements the following optimizations: removal of IN/OUT MOV instructions generated by TGSI and removal of unused instructions when some exports are disabled -ir2 now allows full 8-bit index for constants -ir2_alloc no longer allocates 4 times too many bytes Signed-off-by: Jonathan Marek <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* docs: update calendar 18.2.0-rc1 and 18.2.0-rc2 are outAndres Gomez2018-08-141-13/+1
| | | | Signed-off-by: Andres Gomez <[email protected]>
* radv: Add on-demand compilation of built-in shaders.Bas Nieuwenhuizen2018-08-1413-80/+454
| | | | | | | | | | | | | | | | | | | | | | | | | In environments where we cannot cache, e.g. Android (no homedir), ChromeOS (readonly rootfs) or sandboxes (cannot open cache), the startup cost of creating a device in radv is rather high, due to compiling all possible built-in pipelines up front. This meant depending on the CPU a 1-4 sec cost of creating a Device. For CTS this cost is unacceptable, and likely for starting random apps too. So if there is no cache, with this patch radv will compile shaders on demand. Once there is a cache from the first run, even if incomplete, the driver knows that it can likely write the cache and precompiles everything. Note that I did not switch the buffer and itob/btoi compute pipelines to on-demand, since you cannot really do anything in Vulkan without them and there are only a few. This reduces the CTS runtime for the no caches scenario on my threadripper from 32 minutes to 8 minutes. Reviewed-by: Dave Airlie <[email protected]>
* radv: Refactor blit pipeline creation.Bas Nieuwenhuizen2018-08-141-350/+175
| | | | Reviewed-by: Dave Airlie <[email protected]>
* radv: Make fs key exemplars ordered to be a reverse fs_key lookup.Bas Nieuwenhuizen2018-08-147-88/+39
| | | | | | | While at it, share the exemplars and account for a non-occurring fs key. Reviewed-by: Dave Airlie <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 18:23:44 +0000