summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* radv: add get_image_stride_for_r32g32b32() helperSamuel Pitoiset2018-10-261-10/+17
| | | | | | | For the special R32G32B32 paths. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add create_bview_for_r32g32b32() helperSamuel Pitoiset2018-10-261-33/+38
| | | | | | | For the special R32G32B32 paths. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add create_buffer_from_image() helperSamuel Pitoiset2018-10-261-38/+35
| | | | | | | For the special R32G32B32 paths. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* intel/compiler: Print message descriptor as immediate sourceSagar Ghuge2018-10-261-1/+7
| | | | | | | | | While disassembling send(c) instruction print message descriptor as immediate source operand along with message descriptor. This allows assembler to read immediate source operand and set bits accordingly. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/compiler: Print hex representation along with floating point valueSagar Ghuge2018-10-261-3/+9
| | | | | | | | | | | | | | While encoding the immediate floating point values in instruction we use values upto precision 9, but while disassembling, we print precision to 6 places, which round up the value and gives wrong interpretation for encoded immediate constant. To avoid misinterpretation of encoded immediate values in instruction and disassembled output, print hex representation along with floating point value which can be used by assembler in future. Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* util: Change remaining uint32 cache ids to sha1David McFarland2018-10-265-93/+81
| | | | | | | | | | | | After discussion with Timothy Arceri. disk_cache_get_function_identifier was using only the first byte of the sha1 build-id. Replace disk_cache_get_function_identifier with implementation from radv_get_build_id. Instead of writing a uint32_t it now writes to a mesa_sha1. All drivers using disk_cache_get_function_identifier are updated accordingly. Reviewed-by: Timothy Arceri <[email protected]> Fixes: 83ea8dd99bb1 ("util: add disk_cache_get_function_identifier()")
* freedreno: use fd_bc_alloc_batch instead of fd_batch_create.Hyunjun Ko2018-10-252-2/+2
| | | | | | | | | | Following the commit 2385d7b066 and 8e798e28f7, for resource dependancy tracking. Fixes: dEQP-GLES31.functional.image_load_store.early_fragment_tests.no_early_fragment_tests_depth_fbo with FD_MESA_DEBUG=inorder Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: take reg->num out of union in ir3_registerHyunjun Ko2018-10-251-5/+6
| | | | | | | | | | To avoid wrong result when identifying the type of register. Ie. If the reg is an array, it might be identified as address or predicate register. Fixes: dEQP-GLES31.functional.ssbo.layout.random.arrays_of_arrays.6 Signed-off-by: Rob Clark <[email protected]>
* freedreno/a6xx: disable unused groupsRob Clark2018-10-252-6/+13
| | | | | | | | Don't leave vsconst/fsconst group enabled if we switch to shader with no uniforms. Fixes: abcdf5627a2 freedreno/a6xx: move const emit to state group Signed-off-by: Rob Clark <[email protected]>
* freedreno: add useful assertRob Clark2018-10-251-1/+3
| | | | | | | Would have been useful to catch the problem fixed in 8e798e28f736e22e9e1e4534ab42a36cde14b142 Signed-off-by: Rob Clark <[email protected]>
* swr/rast: ignore CreateElementUnorderedAtomicMemCpyAlok Hota2018-10-251-1/+2
| | | | | | | | | This function's API changed between LLVM 5 and 6. Compile errors occur when building with LLVM 6+ if LLVM 5 was used for a dist tarball CC: <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107865 Reviewed-by: Emil Velikov <[email protected]>
* swr/rast: fix intrinsic/function for LLVM 7 compatibilityAlok Hota2018-10-256-14/+3
| | | | | | | | | | | | Converted from x86 VFMADDPS intrinsic to generic LLVM intrinsic, and removed createInstructionSimplifierPass, which were both removed in LLVM 7.0.0 These changes combine patches we received from the community and our own internal patches Reviewed-by: Bruce Cherniak <[email protected]> Tested-by: Chuck Atkins <[email protected]>
* nvc0: increase NOUVEAU_TRANSFER_PUSHBUF_THRESHOLD to 1024 on Kepler+Rhys Perry2018-10-254-3/+11
| | | | | | | | Gives a +3.89% to +5.27% FPS improvement with Hitman and +2.73% to +2.82% FPS improvement with Dirt Rally on my GTX 1060. Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* radv: Emit enqueued pipeline barriers on event write.Bas Nieuwenhuizen2018-10-251-0/+2
| | | | | | | | | Since the CPU can read them we need to execute any GPU->CPU flushes before the event is written. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108524 Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Add support for VK_KHR_driver_properties.Bas Nieuwenhuizen2018-10-252-0/+25
| | | | Reviewed-by: Jason Ekstrand <[email protected]>
* util: use C99 declaration in the for-loop set_foreach() macroEric Engestrom2018-10-2524-40/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* util: use C99 declaration in the for-loop hash_table_foreach() macroEric Engestrom2018-10-2536-72/+5
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* gen: Add AMD_gpu_shader_int64.xml to tarballDylan Baker2018-10-242-0/+2
| | | | | | | | CC: Ian Romanick <[email protected]> CC: Marek Olšák <[email protected]> Fixes: b3c17330e631695b5e5dc209ba9ea1a528618c97 ("mesa: expose AMD_gpu_shader_int64") Reviewed-by: Juan A. Suarez <[email protected]>
* gen: Add EXT_vertex_attrib_64bit.xml to dependency listsDylan Baker2018-10-242-0/+2
| | | | | | | | | | | Which is also required to put it in the tarball, a requirement for building with meson from the tarball. CC: Ian Romanick <[email protected]> CC: Marek Olšák <[email protected]> Fixes: 263c962cfdee6b43578ee5f28601309ea77d1434 ("mesa: expose EXT_vertex_attrib_64bit") Reviewed-by: Juan A. Suarez <[email protected]>
* anv: move variable to proper scope and mark as MAYBE_UNUSEDEric Engestrom2018-10-241-2/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: use snprintf() instead of memset()+strcpy()Eric Engestrom2018-10-241-4/+3
| | | | | | | | | snprintf() guarantees that it will not write more chars than allowed, and that the string will be null-terminated, without the need to fill the whole thing with zeroes to begin with. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* anv: drop unused includesEric Engestrom2018-10-241-3/+0
| | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* autotools: include intel_tiled_memcopy.cDylan Baker2018-10-242-0/+7
| | | | | | | | | | | | There are two problems with the fixed patch. First, it fails to create a dependency on the sourced .c file, so changes to intel_tiled_memcpy.c won't trigger a rebuild. It also doesn't get included in the dist tarball. Fixes: 11b1afdc92db98e93f2ca50beeb7fc481a11e708 ("i965/tiled_memcpy: inline movntdqa loads in tiled_to_linear") Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Juan A. Suarez <[email protected]>
* meson: fix formatting and add extra_files to i965Dylan Baker2018-10-241-10/+12
| | | | | | | | | | extra_files is just a nice way to to tell certain IDEs (and those reading the file) that this file is also a dependency. Meson will use the .d file generated by the compiler to figure out what the target actually depends on. Reviewed-by: Tapani Pälli <[email protected]> Reviewed-by: Juan A. Suarez <[email protected]>
* ir3_compiler/nir: fix imageSize() for buffer-backed imagesEduardo Lima Mitev2018-10-242-0/+33
| | | | | | | | | | | | | | | | | | | | | | GL_EXT_texture_buffer introduced texture buffers, which can be used in shaders through a new type imageBuffer. Because how image access is implemented in freedreno, calling imageSize on an imageBuffer returns the size in bytes instead of texels, which is incorrect. This patch adds a division of imageSize result by the bytes-per-pixel of the image format, when image is buffer-backed. Fixes all tests under dEQP-GLES31.functional.image_load_store.buffer.image_size.* v2: Pre-compute and submit the log2 of the image format's bpp as shader constant instead of emitting the LOG2 instruction in code. (Rob Clark) v3: Use ffs (find-first-bit) helper for computing log2 (Ilia Mirkin) Reviewed-by: Rob Clark <[email protected]>
* nir: Fix array initializer.Jose Fonseca2018-10-241-1/+1
| | | | | | Empty initializer is not standard C. This fixes MSVC build. Trivial.
* scons: Put to rest zombie texture_float build option.Liviu Prodea2018-10-241-3/+0
| | | | | | | | | | I found a remnant of texture_float build option that wasn't removed in commit 66673bef941af344314fe9c91cad8cd330b245eb This patch removes it. Cc: [email protected] Reviewed-by: Jose Fonseca <[email protected]>
* anv: Allow presenting via a different GPUAlex Smith2018-10-241-2/+2
| | | | | | | | | | | | | | | anv_GetPhysicalDeviceSurfaceSupportKHR will already return success for this, but anv_GetPhysicalDevice{Xcb,Xlib}PresentationSupportKHR do not. Apps which check for presentation support via the latter (all Feral Vulkan games at least) will therefore fail. This allows me to render on an Intel GPU and present to a display connected to an AMD card (tested HD 530 + Vega 64). v2: Rebase on current master. Signed-off-by: Alex Smith <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: fix nir_copy_propagation testJuan A. Suarez Romero2018-10-241-2/+2
| | | | | | | | | | | | | | | Use nir_src_comp_as_uint() to read the proper second component, as nir_src_as_uint() returns the first one. v2: Use nir_src_comp_as_uint() [Jason] Fixes: 16870de8a0a ("nir: Use nir_src_is_const and nir_src_as_* in core code") Signed-off-by: Juan A. Suarez Romero <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108532 Tested-by: Michel Dänzer <[email protected]> Tested-by: Vinson Lee <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: call nir_link_xfb_varyings()Timothy Arceri2018-10-241-0/+4
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: move nir_lower_io_to_scalar_early() to radv_link_shaders()Timothy Arceri2018-10-241-26/+18
| | | | | | | | nir_lower_io_to_scalar_early() is really part of the link time optimisations. Moving it here allows the code to be simplified and also keeps the code easy to follow in the next patch. Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: add linking helper nir_link_xfb_varyings()Samuel Pitoiset2018-10-242-0/+34
| | | | | | | | The linking opts shouldn't try removing or compacting XFB varyings in the consumer. To avoid this we copy the always_active_io flag from the producer. Reviewed-by: Timothy Arceri <[email protected]>
* intel/compiler: Change src1 reg type to unsigned doublewordSagar Ghuge2018-10-232-3/+3
| | | | | | | | | | | To have uniform behavior while disassembling send(c) instruction use register type of unsigned doubleword for src1 when message descriptor is immediate value. Bspec does not specifiy anything for src1 immediate default type. Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Sagar Ghuge <[email protected]>
* mesa/glformats: Remove redundant helper _mesa_base_format_component_countEduardo Lima Mitev2018-10-234-33/+3
| | | | | | | There exists _mesa_components_in_format() which already includes all cases handled in _mesa_base_format_component_count(). Reviewed-by: Tapani Pälli <[email protected]>
* nir/algebraic: Fix a typo in the bit size validation codeJason Ekstrand2018-10-231-2/+2
| | | | | | | | The conon_bit_class and canon_var_class variables got switched. Fixes: 932c650e0b "nir/algebraic: Loosen a restriction on variables" Reported-by: Ian Romanick <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* amd/common: check DRM version 3.27 for JPEG decodeLeo Liu2018-10-231-1/+1
| | | | | | | | | | JPEG was added after DRM version 3.26 Signed-off-by: Leo Liu <[email protected]> Fixes: 4558758c51749(amd/common: add vcn jpeg ip info query) Cc: Boyuan Zhang <[email protected]> Cc: Alex Smith <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* docs: update calendarJuan A. Suarez Romero2018-10-231-2/+2
| | | | | | | | I'll take care of 18.2 releases series on Andres behalf. CC: Andres Gomez <[email protected]> CC: Dylan Baker <[email protected]> CC: Emil Velikov <[email protected]>
* intel/decoders: fix end of batch limitLionel Landwerlin2018-10-233-9/+10
| | | | | | | | | | | | | Pointer arithmetic... v2: s/4/sizeof(uint32_t)/ (Eric) v3: Give bytes to print_batch() in error_decode (Lionel) Make clear what values we're dealing with in error_decode (Lionel) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> (v2) Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: enable vcn jpeg decode for ravenBoyuan Zhang2018-10-231-0/+2
| | | | | | | Enable vcn jpeg decode for raven. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* winsys/amdgpu: add vcn jpeg cs supportBoyuan Zhang2018-10-231-0/+12
| | | | | | | Add vcn jpeg cs support, align cs by no-op. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* amd/common: add vcn jpeg ip info queryBoyuan Zhang2018-10-231-2/+12
| | | | | Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: implement jpeg target buffer cmdBoyuan Zhang2018-10-231-1/+72
| | | | | | | | Implement jpeg target buffer cmd by programming registers directly, since there is no firmware for VCN Jpeg decode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/vcn: implement jpeg bitstream buffer cmdBoyuan Zhang2018-10-231-1/+45
| | | | | | | | Implement jpeg bitstream buffer cmd by programming registers directly, since there is no firmware for VCN Jpeg decode. Signed-off-by: Boyuan Zhang <[email protected]> Acked-by: Leo Liu <[email protected]>
* radeon/uvd: remove get mjpeg slice headerBoyuan Zhang2018-10-231-157/+0
| | | | | | | | Move the previous get_mjpeg_slice_heaeder function and eoi from "radeon/vcn" to "st/va". Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* st/va: get mjpeg slice headerBoyuan Zhang2018-10-233-2/+164
| | | | | | | | Move the previous get_mjpeg_slice_heaeder function and eoi from "radeon/vcn" to "st/va". Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: add jpeg decode implementationBoyuan Zhang2018-10-235-7/+119
| | | | | | | | Add a new file to handle VCN Jpeg decode specific functions. Use Jpeg specific cmd sending function in end_frame call. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: separate send cmd call from end frameBoyuan Zhang2018-10-232-8/+28
| | | | | | | | Use function pointer for sending cmd in end_frame call. By doing this, we can assign different cmd sending logics for Jpeg decode later. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: create cs based on ring typeBoyuan Zhang2018-10-231-2/+6
| | | | | | | Add RING_VCN_JPEG for VCN Jpeg decode, and keep RING_VCN_DEC for other codecs. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/winsys: add vcn jpeg ring typeBoyuan Zhang2018-10-231-0/+1
| | | | | | | Add a new ring type for vcn jpeg. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
* radeon/vcn: add vcn jpeg decode interfaceBoyuan Zhang2018-10-231-0/+90
| | | | | | | Add VCN Jpeg decode interfaces and register defines. Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 13:25:22 +0000