| Commit message (Collapse) | Author | Age | Files | Lines |
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This page is very old and some of the links are dead.
Reviewed-by: Brian Paul <[email protected]>
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This page is very old and some of the links are dead.
Reviewed-by: Brian Paul <[email protected]>
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make it easier to find the docs/autoconf.html site
Reviewed-by: Brian Paul <[email protected]>
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v2: fix typo
Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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replace unordered list <ul> with defined list <dl>
Reviewed-by: Brian Paul <[email protected]>
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replace unordered list <ul> with defined list <dl>
Reviewed-by: Brian Paul <[email protected]>
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removed with commit 56c3cce2a199f7f79a48d7633431e1e80fcd4ba2
two years ago
Reviewed-by: Brian Paul <[email protected]>
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Reviewed-by: Brian Paul <[email protected]>
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v2: use uint64_t for the total_size variable, per Jose.
Also add two earlier checks for exceeding the max texture size.
For example a 1K^3 RGBA volume would overflow the lpr->image_stride
variable.
Use simple algebra to avoid overflow in intermediate values.
So instead of "x * y > z" use "x > z / y".
This should work if we happen to be on a platform that doesn't have
64-bit types.
Reviewed-by: Jose Fonseca <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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This was already (correctly) supported for glGetSamplerParameter paths.
NOTE: This is a candidate for stable branches.
Signed-off-by: Ian Romanick <[email protected]>
Reviewed-by: Brian Paul <[email protected]>
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Initializing the regalloc state is expensive, and since it is always
the same for every compile we only need to initialize it once per
context. This should help improve shader compile times for the driver.
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This allows the user to pass precomputed q values to the allocator.
Reviewed-by: Kenneth Graunke <[email protected]>
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Reviewed-by: Kenneth Graunke <[email protected]>
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Compute shaders fetch data from vertex buffers via the texture cache, so
we need to make sure the texture cache is flushed.
v2:
- Fix rebase mistake
- Fix spelling in comment
Reviewed-by: Marek Olšák <[email protected]>
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LOOP_START_DX10 ignores the LOOP_CONFIG* registers, so it is not limited
to 4096 iterations like the other LOOP_* instructions. Compute shaders
need to use this instruction, and since we aren't optimizing loops with
the LOOP_CONFIG* registers for pixel and vertex shaders, it seems like
we should just use it for everything.
Reviewed-by: Marek Olšák <[email protected]>
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For buffers (which is what is being used for RATs), the
COLOR*_DIM.WIDTH_MASK field needs to be set to the low 16-bits of the
buffer size, and the COLOR*_DIM.HEIEGHT_MAX needs to be set to the
high bits.
Reviewed-by: Marek Olšák <[email protected]>
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The kernel CS checker will fail if this register is not initialized.
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Marek Olšák <[email protected]>
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Signed-off-by: Tom Stellard <[email protected]>
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This is necessary upcoming encoding changes, since we will only be
using 9-bits for register encoding.
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- add OpenCL state tracker Clover
- add XvMC state tracker
- remove progs
directory got moved into its own repository mesa/demos
- remove vf
directory removed with abda64efce73c18d49c74
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This reverts commit 5b807400a87d5efefc481017eb420b772933e1da.
accidentally pushed.
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This reverts commit 5205db6a7ce623a7fca72e6dc6391bd12be3f6aa.
accidentally pushed
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This reverts commit 0c67fe5d2dc6d8066fc23c39184d9614abf63992.
accidentally pushed.
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This is the code that checks if a subtexure region is aligned to the
compressed format's block size.
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I have left the links as <code> elements for the purpose of
documentation.
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improve markup
fix link to relnotes-9.0
add missing relnotes links
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Don't cache pointers to elements of reallocatable array.
In some circumstances it caused false cache hits resulting in incorrect
command stream and gpu lockup.
Note: This is a candidate for the stable branches.
Signed-off-by: Vadim Girlin <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
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Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
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Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
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