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* nv50: rebind bo to bufctx when invalidating idxbuf storageIlia Mirkin2015-09-061-1/+5
| | | | | | | | | There is nothing to be done on a dirty idxbuf, but the bo may have changed, so we have to rebind it to the bufctx. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] (cherry picked from commit 1f62d36ae21043c472fc182fd4b738ec1d54a2d2)
* nv50: clear buffer status on all vertex bufs, not just the first oneIlia Mirkin2015-09-061-1/+0
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] (cherry picked from commit 114cc18b98b6e016ab1986577aa3df12acc22cca)
* nv50: fix drawing from tfb, direct-to-pushbuf submitsIlia Mirkin2015-09-064-14/+15
| | | | | | | | | | | | The stride was being set to 0, which is illegal (and also non-sensical). Also we must wait for the buffer to become available for reading as otherwise a wrong value may be prefetched. Since we must wait for the buffer anyways, and it's mapped and in GART, we may as well avoid the annoyance of the indirect pushbuf submit. Signed-off-by: Ilia Mirkin <[email protected]> Cc: [email protected] (cherry picked from commit 75e34d1df8b0ab56e5e658b8ef90ff6057ec954e)
* llvmpipe: convert double to long long instead of unsigned long longOded Gabbay2015-09-061-1/+1
| | | | | | | | | | | | | | | | | | round(val*dscale) produces a double result, as val and dscale are double. However, LLVMConstInt receives unsigned long long, so there is an implicit conversion from double to unsigned long long. This is an undefined behavior. Therefore, we need to first explicitly convert the round result to long long, and then let the compiler handle conversion from that to unsigned long long. This bug manifests itself in POWER, where all IMM values of -1 are being converted to 0 implicitly, causing a wrong LLVM IR output. Signed-off-by: Oded Gabbay <[email protected]> CC: "10.6 11.0" <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> (cherry picked from commit 4f2290d1612569686284609059d29a85c9de67cf)
* nv30: Implement color resolve for msaaHans de Goede2015-09-062-14/+8
| | | | | | | | | | | | Note this is not ideal. Since the sifm can only do source sizes upto 1024x1024 we end up using the blitter on nv4x, which is not that fast. And on nv3x we end up using the cpu which is really slow. Cc: "10.6 11.0" <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (cherry picked from commit 3c6c4d4f298ec81fe57992790a68aaab2e573519)
* nv30: Fix creation of scanout buffersHans de Goede2015-09-061-0/+10
| | | | | | | | | | | | | | | | | | | | | | Scanout buffers on nv30 must always be non-swizzled and have special width alignment constraints. These constrains have been taken from the xf86-video-nouveau src/nv_accel_common.c: nouveau_allocate_surface() function. nouveau_allocate_surface() applies these width constraints only when a tiled attribute is set, which it sets for all surfaces allocated via dri, and this "tiling" is not the same as swizzling, scanout surfaces must be linear / have a uniform_pitch or only complete garbage is shown. This commit fixes dri3 on nv30 showing a garbled display, with dri3 the scanout buffers are allocated by mesa, rather then by the ddx, and the wrong stride of these buffers was causing the garbled display. Cc: "10.6 11.0" <[email protected]> Signed-off-by: Hans de Goede <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (cherry picked from commit 3329703eb116a7ad73bc694356b43e014532240b)
* vc4: Initialize pack field of qreg to 0 in qir_get_tempBoyan Ding2015-09-061-0/+1
| | | | | | | | | | | | | | This avoids generation of undefined packing in qir and qpu instructions, fixing a lot of rendering errors. Fixes 8b36d107fdd (vc4: Pack the unorm-packing bits into a src MUL instruction when possible.) Cc: [email protected] Signed-off-by: Boyan Ding <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Emil Velikov <[email protected]> (cherry picked from commit 48de40ce9c45de154965490843f9e50407970c26)
* i965: Disallow PixelTransfer operations for tiled-memcpy TexImage/ReadPixelsChris Wilson2015-09-062-0/+8
| | | | | | | | | | | | | | | | The tiled memcpy fast paths perform a simple blit (with only a couple of trivial pixel conversion routines) and do not accommodate PixelTransfer operations. Therefore if any are set, fallback to the regular routines. Note that PixelTransfer only applies to TexImage and ReadPixels, not to GetTexImage. Signed-off-by: Chris Wilson <[email protected]> Cc: Jason Ekstrand <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Cc: [email protected] (cherry picked from commit 099f5b3a62be1919add02a4cb887841c9f0f2fe4)
* i965: Fix copy propagation type changes.Kenneth Graunke2015-09-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | commit 472ef9a02f2e5c5d0caa2809cb736a0f4f0d4693 introduced code to change the types of SEL and MOV instructions for moves that simply "copy bits around". It didn't account for type conversion moves, however. So it would happily turn this: mov(8) vgrf6:D, -vgrf5:D mov(8) vgrf7:F, vgrf6:UD into this: mov(8) vgrf6:D, -vgrf5:D mov(8) vgrf7:D, -vgrf5:D which erroneously drops the conversion to float. Cc: "11.0 10.6" <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Matt Turner <[email protected]> (cherry picked from commit 2ace64fd598816fd1be9877962734242fc27b87b)
* winsys/radeon: remove exported buffers from the cacheMarek Olšák2015-09-061-0/+3
| | | | | | Cc: 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (cherry picked from commit efea7c3a3f91219db6e2fa3588388b6be4ecfa40)
* winsys/amdgpu: remove exported buffers from the cacheMarek Olšák2015-09-061-0/+3
| | | | | | Cc: 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (cherry picked from commit 54964c77510b060806615c842692c0f393e807e6)
* gallium/pb_bufmgr_cache: add a way to remove buffers from the cache explicitlyMarek Olšák2015-09-062-6/+41
| | | | | | | | | This must be done before exporting a buffer as dmabuf fds, because we lose track of who is using it and can't trust the reference counter. Cc: 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (cherry picked from commit 35d0f12797237cdd38e7fd2c39d3c19e875875ca)
* glsl: Handle attribute aliasing in attribute storage limit check.Kenneth Graunke2015-09-061-28/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | In various versions of OpenGL and GLSL, it's possible to declare multiple VS input variables with aliasing attribute locations. So, when computing the storage requirements for vertex attributes, we can't simply add up the sizes. Instead, we need to look at the enabled slots. This patch begins tracking which attributes are double types that are larger than 128-bits (i.e. take up two vec4 slots). We then count normal attributes once, and count the double-size attributes a second time. Fixes deQP functional.attribute_location.bind_aliasing.max_cond_* tests on i965, which regressed with commit ad208d975a6d3aebe14f7c2c16039ee20. No Piglit changes on llvmpipe (which actually supports dvecs). Cc: "10.6 11.0" <[email protected]> Tested-by: Mark Janes <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]> (cherry picked from commit c3294ca5a13cf3f0eb3d9907a46ff8ce4bc2963b)
* mesa: Don't allow wrong type setters for matrix uniformsIan Romanick2015-09-061-0/+25
| | | | | | | | | | | | | | Previously we would allow glUniformMatrix4fv on a dmat4 and glUniformMatrix4dv on a mat4. Both are illegal. That later also overwrites the storage for the mat4 and causes bad things to happen. Should fix the (new) arb_gpu_shader_fp64-wrong-type-setter piglit test. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Cc: Dave Airlie <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 7237c937af3b495191bee2f7240901e3a9daf1fb)
* mesa: Pass the type to _mesa_uniform_matrix as a glsl_base_typeIan Romanick2015-09-063-42/+42
| | | | | | | | | | | | | This matches _mesa_uniform, and it enables the bug fix in the next patch. v2: s/type/basicType/ in the assert in _mesa_uniform_matrix. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> [v1] Cc: Dave Airlie <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit a6976f09727014730f45ec27c714c6a8140e074a)
* i965/fs: Handle MRF destinations in lower_integer_multiplication().Matt Turner2015-09-061-4/+4
| | | | | | | | | | | | | | | | | The lowered code reads from the destination, which isn't possible from message registers. Fixes the following dEQP tests on SNB: dEQP-GLES3.functional.shaders.precision.int.highp_mul_fragment dEQP-GLES3.functional.shaders.precision.int.mediump_mul_fragment dEQP-GLES3.functional.shaders.precision.int.lowp_mul_fragment Cc: "10.6 11.0" <[email protected]> Tested-by: Mark Janes <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 9390cb84593bda516e8c1521c87a08475574d1be)
* mesa/readpixels: check strides are equal before skipping conversionDave Airlie2015-09-061-1/+2
| | | | | | | | | | | | | | The CTS packed_pixels test checks that readpixels doesn't write into the space between rows, however we fail that here unless we check the format and stride match. This fixes all the core mesa problems with CTS packed_pixels tests. Cc: "11.0" <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 32769ac016dee4ce5767a922f91de47df4ce984d)
* texcompress_s3tc/fxt1: fix stride checks (v1.1)Dave Airlie2015-09-062-5/+5
| | | | | | | | | | | | | | | | | | | The fastpath currently checks the RowLength != width, but if you have a RowLength of 7, and Alignment of 4, then that shouldn't match. align the rowlength to the pack alignment before comparing. This fixes compressed cases in CTS packed_pixels_pixelstore test when SKIP_PIXELS is enabled, which causes row length to get set. v1.1: add fxt1 fix (Iago) Cc: "11.0" <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit b4a70401f52e5d7e08c94715b250ea1de8f63d15)
* st/readpixels: fix accel path for skipimages.Dave Airlie2015-09-061-2/+2
| | | | | | | | | | | | | | | We don't need to use the 3d image address here as that will include SKIP_IMAGES, and we are only blitting a single 2D anyways, so just use the 2D path. This fixes some memory overruns under CTS packed_pixels.packed_pixels_pixelstore when PACK_SKIP_IMAGES is used. Cc: "11.0" <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 6a3e1fb958778e00e8fe2d860b6327fc4409c148)
* mesa/formats: 8-bit channel integer formats additionDave Airlie2015-09-065-0/+64
| | | | | | | | | | Add enough 8-bit channel formats to handle all the different things CTS throws at us. Cc: "11.0" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit c3c242070e868225a81e1afe5fb424c33eb94c2f)
* mesa/formats: add some formats from GL3.3Dave Airlie2015-09-065-0/+123
| | | | | | | | | | | | | | | | | GL3.3 added GL_ARB_texture_rgb10_a2ui, which specifies a lot more things than just rgb10/a2ui. While playing with ogl conform one of the tests must attempted all valid formats for GL3.3 and hits the unreachable here. This adds the first chunk of formats that hit the assert. Cc: "11.0" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 8185a02316cfb7dc3d64b8772af82ad2bb49754e)
* mesa: handle SwapBytes in compressed texture get code.Dave Airlie2015-09-061-0/+7
| | | | | | | | | This case just wasn't handled, so add support for it. Cc: "11.0" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 5b6c7da460b8f6c908df7060ec0709a9848ce160)
* mesa: fix SwapBytes handling in numerous placesDave Airlie2015-09-066-56/+89
| | | | | | | | | | | | | | | | | | | | In a number of places the SwapBytes handling didn't handle cases with GL_(UN)PACK_ALIGNMENT set and 7 byte width cases aligned to 8 bytes. This adds a common routine to swap bytes a 2D image and uses this code in: texture storage texture get readpixels swrast drawpixels. [airlied: updated with Brian's nitpicks]. Cc: "11.0" <[email protected]> Reviewed-by: Brian Paul <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 0ad3a475ef81dad3baf607d749b91dfa1700ca23)
* radeonsi: fix memory usage checking for big IBsMarek Olšák2015-09-061-8/+9
| | | | | | | Cc: 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> (cherry picked from commit 05af645a951fd985d0dbe3c22614e1dee8dfb3f0)
* radeonsi: set all 16 viewport Z bounds for GL 4.1Marek Olšák2015-09-061-2/+6
| | | | | | | Cc: 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> (cherry picked from commit 08775a219628611989ab87c621255ac3c841dcda)
* radeonsi: fix a Unigine Heaven hang when drirc is missingMarek Olšák2015-09-064-1/+28
| | | | | | | Cc: 10.6 11.0 <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> (cherry picked from commit 9b510a9652297a63677f1d55b2bf444694fd94e1)
* i965: Prevent coordinate overflow in intel_emit_linear_blitChris Wilson2015-09-061-38/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes regression from commit 8c17d53823c77ac1c56b0548e4e54f69a33285f1 Author: Kenneth Graunke <[email protected]> Date: Wed Apr 15 03:04:33 2015 -0700 i965: Make intel_emit_linear_blit handle Gen8+ alignment restrictions. which adjusted the coordinates to be relative to the nearest cacheline. However, this then offsets the coordinates by up to 63 and this may then cause them to overflow the BLT limits. For the well aligned large transfer case, we can use 32bpp pixels and so reduce the coordinates by 4 (versus the current 8bpp pixels). We also have to be more careful doing the last line just in case it may exceed the coordinate limit. Reported-and-tested-by: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90734 Signed-off-by: Chris Wilson <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ian Romanick <[email protected]> Cc: Anuj Phogat <[email protected]> Cc: [email protected] Reviewed-by: Anuj Phogat <[email protected]> (cherry picked from commit d38a5601068ae1d923efece8f28757777f4474e4)
* r600g: fix calculation for gpr allocationDave Airlie2015-09-061-1/+1
| | | | | | | | | | | | | | | | I've been chasing a geom shader hang on rv635 since I wrote r600 geom code, and finally I hacked some values from fglrx in and I could run texelfetch without failures. This is totally my fault as well, maths fail 101. This makes geom shaders on r600 not fail heavily. Cc: "10.6" "11.0" <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 0de53ccc8cbee0f63ba25c9e72664b3cbd31be54)
* r600/sb: update last_cf for finalize if.Dave Airlie2015-09-061-0/+3
| | | | | | | | | | | | | As Glenn did for finalize_loop we need to update_cf when we add a POP at the end of a shader. I think this fixes one of the earlier shader going off end of memory problems we've stopped. Reviewed-by: Glenn Kennard <[email protected]> Cc: "10.6" "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 3063913f77cd2db1a263cb824a5c8c3dcc1a51a0)
* egl: scons: fix the haiku build, do not build the dri2 backendAlexander von Gluck IV2015-09-011-1/+0
| | | | | | Reviewed-by: Emil Velikov <[email protected]> (cherry picked from commit 5abbd1caccf4653ac1a8760de68d8ed101c814d8) Fixes: 78674631a2d(egl: remove the non-haiku scons build)
* freedreno/a4xx: formats updateRob Clark2015-09-011-5/+5
| | | | | | | Fixes glamor, which wants to use R8 integer textures. Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit 000e225360c020e8b3de142c4c898baad321d242)
* freedreno: update generated headersRob Clark2015-09-015-5/+8
| | | | | Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit afb6c24a207fe7b9917644b940e4c5d1870c5c92)
* r600: move prim convert from geom shader to function.Dave Airlie2015-09-012-25/+26
| | | | | | | | | | This should avoid C++ fail including this header. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 03b7ec877843cd622717b01c1047e08baf34facf) Fixes: 69418831756 (r600: port si_conv_prim_to_gs_out from radeonsi) Nominated-by: Marek Olšák <[email protected]>
* Update version to 11.0.0-rc2mesa-11.0.0-rc2Emil Velikov2015-08-311-1/+1
| | | | Signed-off-by: Emil Velikov <[email protected]>
* gallium/radeon: fix the ADDRESS_HI mask for EVENT_WRITE CIK packetsMarek Olšák2015-08-311-8/+8
| | | | | | Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]> (cherry picked from commit 437cb1e3f482570447501526927df4d80c845bf5)
* freedreno/a3xx: add basic clip plane supportIlia Mirkin2015-08-313-1/+24
| | | | | | | | | | The hardware is capable of dealing with GL1-style user clip planes. No clip vertex, no clip distances. Fixes a number of ucp tests, as well as neverball. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]> (cherry picked from commit 58e24b4761ec8c348bf6825c2355a6e047599306)
* r600: port si_conv_prim_to_gs_out from radeonsiDave Airlie2015-08-311-15/+16
| | | | | | | | | | This code was broken by the tess merge, and I totally missed it until now. I'm not sure this fixes anything but it stops the assert. Cc: "11.0" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 6941883175612ae602a8745945153ba064f53a7a)
* gallium/util: fix debug_get_flags_option on 32-bitDave Airlie2015-08-311-3/+4
| | | | | | | | | | On 32-bit we need to use PRIu64 flags for printfs, otherwise this segfaults in R600_DEBUG=help otherwise. Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 8d6d0cc17d945317f44328a7761801e6781dc3fc)
* mesa: add missing queries for ARB_direct_state_accessDaniel Scharrer2015-08-312-0/+98
| | | | | | | | | | | | This adds index queries (glGet*i_v) for GL_TEXTURE_BINDING_* and GL_SAMPLER_BINDING, as well as textue queries (glGetTex{,ture}Parameter*) for GL_TEXTURE_TARGET. CC: "10.6 11.0" <[email protected]> Reviewed-by: Fredrik Höglund <[email protected]> Signed-off-by: Fredrik Höglund <[email protected]> (cherry picked from commit 5aaaaebf22c920745d577c49e463d23b90ba5ea8)
* r600g/sb: Don't crash on empty if jump targetGlenn Kennard2015-08-311-1/+4
| | | | | | | Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 608c7b4a63d5818f7ae0b3d48496b02cf8458d9b)
* r600g/sb: Don't read junk after EOPGlenn Kennard2015-08-313-1/+6
| | | | | | | | | | | | | | Shaders that contain instruction data after an instruction with EOP could end up parsing that as an instruction, leading to various crashes and asserts in SB as it gets very confused if it sees for instance a loop start instruction jumping off to some random point. Add a couple of asserts, and print EOP bit if set in old asm printer. Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit a830225adbb77073272961df409885cca6b861ee)
* r600g/sb: Handle undef in read port trackerGlenn Kennard2015-08-311-1/+1
| | | | | | | | | | e8e443 missed adding check for undef values also in unreserve function, leading to an assert triggering. Signed-off-by: Glenn Kennard <[email protected]> Cc: <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 36f1999a87258603b6720d55e6020d5d24c215c9)
* mesa: only copy the requested teximage facesIlia Mirkin2015-08-311-2/+2
| | | | | | | | | | | | | | | Cube maps are special in that they have separate teximages for each face. We handled that by copying the data to them separately, but in case zoffset != 0 or depth != 6 we would read off the end of the client array or modify the wrong images. zoffset/depth have already been verified by the time the code gets to this stage, so no need to double-check. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 2259b111003f2e8c55cae42677ec45345fb1b6e3)
* i965/fs: Split VGRFs after lowering pull constantsJason Ekstrand2015-08-311-2/+2
| | | | | | | | | | | | | | The split_virtual_grfs code doesn't properly rewrite reladdr so we need to make sure that any uniform indirects are lowered away first. This fixes the glsl-fs-uniform-indexed-by-swizzled-vec4.shader_test in piglit Cc: "10.6" <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit fee0c5af11dd0995de96e7053377d425a66d03a0) Conflicts: src/mesa/drivers/dri/i965/brw_fs.cpp
* mesa: create multisample fallback textures like normal texturesMarek Olšák2015-08-311-0/+2
| | | | | | | | | | This works if drivers upsample on upload (like all radeon ones do). The alternative is an unexpected GL error from anything calling _mesa_update_state and possibly other issues. Cc: 10.6 11.0 <[email protected]> Reviewed-by: Dave Airlie <[email protected]> (cherry picked from commit f432ae899fb81468778dbeb17ac7615da3ed5c0d)
* mesa/texgetimage: fix missing stencil checkDave Airlie2015-08-311-0/+7
| | | | | | | | | | | | | GetTexImage can read to stencil8 but only from a stencil or depthstencil textures. This fixes a bunch of failures in CTS GL33-CTS.gtf32.GL3Tests.packed_pixels Reviewed-by: Marek Olšák <[email protected]> Cc: "11.0" <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit c1452983b44cc8ee238b8c7e2cfca1105c707487)
* mesa: enable texture stencil8 for multisampleDave Airlie2015-08-311-2/+5
| | | | | | | | | | This fixes GL45-CTS.gtf44.GL31Tests.texture_stencil8.texture_stencil8_gl44 from the ogl conform suite. Reviewed-by: Ilia Mirkin <[email protected]> Cc: 10.6 11.0 <[email protected]> Signed-off-by: Dave Airlie <[email protected]> (cherry picked from commit 529acab22a3e21e0ed0c5243675aec6c0ee27e8f)
* i965: Always re-emit the pipeline select during invariant state emissionChris Wilson2015-08-311-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the older platforms where we don't have logical contexts preserving state across batches, we emit the invariant state setup on every batch using the brw_invariant_state atom. This includes the pipeline selection which is cached with the introduction of commit 0e0e23ef537c9add672ff322f34e129a07edc55e Author: Jordan Justen <[email protected]> Date: Wed Apr 22 11:43:50 2015 -0700 i965/state: Emit pipeline select when changing pipelines However, we do not reset the cache between batches on context-less platforms resulting in us not setting the pipeline selection and can cause GPU hangs if a media pipelined was loaded in the meantime (e.g. mixing mplayer/gstreamer using libva and gnome-shell). A simple solution is to just forcibly re-emit the pipeline select along with the invariant state and reset the cache at that point. Reported-and-tested-by: Tomasz C. <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91254 Signed-off-by: Chris Wilson <[email protected]> Cc: Jordan Justen <[email protected]> Cc: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Cc: "10.6 11.0" <[email protected]> (cherry picked from commit 4e5752e2b78243a71766538f62ca0a80488047a7)
* Revert "radeon/winsys: increase the IB size for VM"Marek Olšák2015-08-314-17/+6
| | | | | | | | | | This reverts commit 567394112d904096abff1d994ab952f475dfb444. It regressed performance. It looks like smaller IBs are better, because the GPU goes idle quicker and there is less waiting for buffers and fences. Cc: 11.0 <[email protected]> (cherry picked from commit a83c36b5c0c64c717ced76db89bab900006648aa)
* nv50: fix 2d engine blits for 64- and 128-bit formatsIlia Mirkin2015-08-311-0/+4
| | | | | | | | This fixes bin/ext_framebuffer_multisample-formats all_samples Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]> (cherry picked from commit e18c29b03105567cf20bc235ce23cf08986cc537)
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