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* radv: enable VK_AMD_shader_trinary_minmax extensionDaniel Schürmann2018-03-292-0/+2
| | | | | Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* ac: add support for trinary_minmax instructionsDaniel Schürmann2018-03-291-0/+54
| | | | | | | v2: Add missing break (Bas) Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* spirv: add support for SPV_AMD_shader_trinary_minmaxDave Airlie2018-03-294-0/+58
| | | | | | | Co-authored-by: Daniel Schürmann <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nir: add support for min/max/median of 3 srcsDave Airlie2018-03-291-0/+14
| | | | | | | | | | | These are needed for SPV_AMD_shader_trinary_minmax, the AMD HW supports these. Co-authored-by: Daniel Schürmann <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: simplify DCC format categoriesMarek Olšák2018-03-281-20/+9
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't use the SPI barrier management bug workaroundMarek Olšák2018-03-281-0/+5
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: use maximum OFFCHIP_BUFFERING on Vega12Marek Olšák2018-03-281-1/+8
| | | | Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/nir: Add workaround for GFX9 buffer views.Bas Nieuwenhuizen2018-03-295-7/+70
| | | | | | | | | | | | | | | | | | | | | On GFX9 whether the buffer size is interpreted as elements or bytes depends on whether IDXEN is enabled in the instruction. If the index is a constant zero, LLVM optimizes IDXEN to 0. Now the size in elements is interpreted in bytes which of course results in out of bounds accesses. The correct fix is most likely to disable the LLVM optimization, but we need something to work with LLVM <= 6.0. radeonsi does the max between stride and element count on the CPU but that results in the size intrinsics returning the wrong size for the buffer. This would cause CTS errors for radv. v2: Also include the store changes. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Samuel Pitoiset <[email protected]>
* ac/surface: set AddrSurfInfoIn.format = ADDR_FMT_8 for stencil, add assertionsMarek Olšák2018-03-281-0/+8
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105738 Tested-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: enable VK_EXT_sampler_filter_minmaxSamuel Pitoiset2018-03-281-0/+1
| | | | | | | Only enable for CIK+ because it's buggy on SI. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add support for VK_EXT_sampler_filter_minmaxSamuel Pitoiset2018-03-282-1/+70
| | | | | | | The driver only supports the required formats for now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename VEGA10 device nameSamuel Pitoiset2018-03-281-1/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add support for Vega12Samuel Pitoiset2018-03-283-1/+6
| | | | | | | Based on RadeonSI. Untested. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* build: Fix up nir_intrinsics.PloMatt Turner2018-03-281-0/+3
| | | | | | | | | | | | | nir_intrinsics.c existed as a static file until commit 76dfed8ae2d5 began generating it as part of the build process. autotools is incapable of coping, and so a build-tree from before this commit would then fail with it: [4]: *** No rule to make target '../../../mesa/src/compiler/nir/nir_intrinsics.c', needed by 'nir/nir_intrinsics.lo'. Stop. Add a few lines to configure.ac to update the broken build files. Fixes: 76dfed8ae2d5 ("nir: mako all the intrinsics")
* autotools: Include intel/dev/meson.build in tarballDylan Baker2018-03-281-0/+1
| | | | | | | Fixes: 272bef0601a1bdb5292771aefc8d62fcbdf4c47f ("intel: Split gen_device_info out into libintel_dev") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* autotools: include meson_get_versionDylan Baker2018-03-281-1/+2
| | | | | | | | | | Otherwise meson won't read the VERSION file and won't set a version. That means that pkg-config files will have version unset as well. Fixes: 3e9533d9b88d75d99632fa40e38cfed842d10842 ("meson: Add script to use VERSION file for getting version") Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: fix 18.0 release note versionEric Engestrom2018-03-281-4/+4
| | | | | | | Fixes: 839fb3a696679bfe975c2 "docs: Update 18.0.0 release notes" Cc: "18.0" <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* radeonsi: add support for Vega12Marek Olšák2018-03-288-8/+41
| | | | Reviewed-by: Alex Deucher <[email protected]>
* amd/addrlib: update to the latest version for Vega12Marek Olšák2018-03-2817-148/+439
| | | | Reviewed-by: Alex Deucher <[email protected]>
* gbm: remove never-implemented functionEric Engestrom2018-03-282-3/+0
| | | | | | | | | | I assume this was implemented in a previous version of that commit, but was removed in the version that actually landed. Fixes: 8430af5ebe1ee8119e14 "Add support for swrast to the DRM EGL platform" Cc: Giovanni Campagna <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* android: Use new nir intrinsics python scriptsStefan Schake2018-03-281-0/+9
| | | | | | | Fixes: 76dfed8ae2d5 ("nir: mako all the intrinsics") Signed-off-by: Stefan Schake <[email protected]> Acked-by: Rob Clark <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* broadcom/vc5: Fix padding of NPOT miplevels >= 2.Eric Anholt2018-03-271-3/+8
| | | | | | | The power-of-two padded size that gets minified is based on level 1's dimensions, not level 0's, which starts to differ at a width of 9. Fixes all failures on texelFetch fs sampler2D 1x1x1-64x64x1
* ac/radeonsi: pass bindless bool to load_sampler_desc()Timothy Arceri2018-03-284-5/+14
| | | | | | | | We also fix the base_index for bindless by using the driver location. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir: set driver location for bindless images and samplersTimothy Arceri2018-03-281-1/+2
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: set uses_bindless_samplers for samplersTimothy Arceri2018-03-281-0/+3
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* nir: add bindless to nir dataTimothy Arceri2018-03-282-0/+7
| | | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* i965: Drop unnecessary bo->align field.Kenneth Graunke2018-03-273-10/+0
| | | | | | | | bo->align is always 0; there's no need to waste 8 bytes storing it. Thanks to C99 initializers zeroing fields, we can completely drop the only read of the field altogether. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop unused alignment parameter from brw_bo_alloc().Kenneth Graunke2018-03-2714-26/+25
| | | | | | brw_bo_alloc no longer uses this parameter, so there's no point. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop alignment parameter from bo_alloc_internal().Kenneth Graunke2018-03-271-7/+6
| | | | | | | | | | | Buffers are always page aligned on 965+ hardware; I believe this extra parameter is a vestige from the Gen2-3 era. All callers pass 0, and in fact we assert that the alignment is 0 unless BO_ALLOC_BUSY is set (for some reason). We can just drop the parameter and set the value to 0 explicitly. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop BO_ALLOC_BUSY in intel_miptree_create_for_bo().Kenneth Graunke2018-03-271-2/+2
| | | | | | | intel_miptree_create_for_bo does not actually allocate a BO, so specifying allocation flags accomplishes nothing and is confusing. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Drop PIPE_CONTROL_NO_WRITE from various calls.Kenneth Graunke2018-03-274-11/+4
| | | | | | | This is just zero - passing nothing already gives us a post-sync operation of "nothing". Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/intrinsics: Don't report negative dest_componentsJason Ekstrand2018-03-271-1/+1
| | | | | | | | I have no idea why but having dest_components == -1 was causing a memory leak somewhere. Without this, you can't get through a full shader-db run without running out of memory. Reviewed-by: Rob Clark <[email protected]>
* intel/fs: Don't emit a des copy for image ops with has_dest == falseJason Ekstrand2018-03-271-3/+6
| | | | | | | | | | This was causing us to walk dest_components times over a thing with no destination. This happened to work because all of the image intrinsics without a destination also happened to have dest_components == 0. We shouldn't be reading dest_components if has_dest == false. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nvc0/ir: fix INTERP_* with indirect inputsIlia Mirkin2018-03-271-3/+4
| | | | | | | | | | | | There were two problems, both of which are fixed now: - The indirect address was not being shifted by 4 - The indirect address was being placed as an argument in the offset case This fixes some of the new interpolateAt* piglits which now test for these situations. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Karol Herbst <[email protected]>
* nir: fix crash in loop unroll corner caseTimothy Arceri2018-03-281-5/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When an if nesting inside anouther if is optimised away we can end up with a loop terminator and following block that looks like this: if ssa_596 { block block_5: /* preds: block_4 */ vec1 32 ssa_601 = load_const (0xffffffff /* -nan */) break /* succs: block_8 */ } else { block block_6: /* preds: block_4 */ /* succs: block_7 */ } block block_7: /* preds: block_6 */ vec1 32 ssa_602 = phi block_6: ssa_552 vec1 32 ssa_603 = phi block_6: ssa_553 vec1 32 ssa_604 = iadd ssa_551, ssa_66 The problem is the phis. Loop unrolling expects the last block in the loop to be empty once we splice the instructions in the last block into the continue branch. The problem is we cant move phis so here we lower the phis to regs when preparing the loop for unrolling. As it could be possible to have multiple additional blocks/ifs following the terminator we just convert all phis at the top level of the loop body for simplicity. We also add some comments to loop_prepare_for_unroll() while we are here. Fixes: 51daccb289eb "nir: add a loop unrolling pass" Reviewed-by: Jason Ekstrand <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670
* st/glsl_to_nir: correctly handle arrays packed across multiple varsTimothy Arceri2018-03-281-1/+23
| | | | | | | Fixes piglit test: tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-interleave-range.shader_test Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix input processing for packed varyingsTimothy Arceri2018-03-281-3/+2
| | | | | | | | | The location was only being incremented the first time we processed a location. This meant we would incorrectly skip some elements of an array if the first element was packed and proccessed previously but other elements were not. Reviewed-by: Marek Olšák <[email protected]>
* ac/nir_to_llvm: fix component packing for double outputsTimothy Arceri2018-03-281-1/+3
| | | | | | | | | | We need to wait until after the writemask is widened before we adjust it for component packing. Together with the previous patch this fixes a number of arb_enhanced_layouts component layout piglit tests. Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir: fix driver location for dual-slot packed doublesTimothy Arceri2018-03-281-6/+16
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: fix scanning of multi-slot output varyingsTimothy Arceri2018-03-281-109/+127
| | | | | | | | | | This fixes tcs/tes varying arrays where we dont lower indirects and therefore don't split arrays. Here we also fix useagemask for dual slot doubles. Fixes a number of arb_tessellation_shader piglit tests. Reviewed-by: Marek Olšák <[email protected]>
* broadcom/vc5: Fix RG16I/UI texture sampling.Eric Anholt2018-03-271-2/+2
| | | | | | | How many times did I look at this table without noticing the missing 'G' in the texture column? Fixes KHR-GLES3.copy_tex_image_conversions.required.* on 7268.
* nir: fix generated nir_intrinsics.c for MSVCRob Clark2018-03-271-0/+4
| | | | | | | | | | Apparently it is not happy about things like: .foo = {} So skip over initializers for empty lists. Fixes: 76dfed8ae2d5c6c509eb2661389be3c6a25077df Reported-by: Roland Scheidegger <[email protected]> Signed-off-by: Rob Clark <[email protected]>
* docs: update calendar 18.0.0 is outEmil Velikov2018-03-271-22/+4
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add news item and link release notes for 18.0.0Emil Velikov2018-03-272-0/+8
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: add sha256 checksums for 18.0.0Emil Velikov2018-03-271-1/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit fb64913d195112462786c0459d12f4bc8e7adee7)
* docs: Update 18.0.0 release notesEmil Velikov2018-03-272-74/+320
| | | | | | | | Note: the file was originally 17.4.0, yet git stuggles to detect the move :-\ Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit dceb1ce807a8b0ab32dc16b38040969bdbcc0d1b)
* nir: mako all the intrinsicsRob Clark2018-03-2711-619/+727
| | | | | | | | | | | | | | | | | | | | | | | I threatened to do this a long time ago.. I probably *should* have done it a long time ago when there where many fewer intrinsics. But the system of macro/#include magic for dealing with intrinsics is a bit annoying, and python has the nice property of optional fxn params, making it possible to define new intrinsics while ignoring parameters that are not applicable (and naming optional params). And not having to specify various array lengths explicitly is nice too. I think the end result makes it easier to add new intrinsics. v2: couple small fixes found with a test program to compare the old and new tables v3: misc comments, don't rely on capture=true for meson.build, get rid of system_values table to avoid return value of intrinsic() and *mostly* remove side-effects, add autotools build support v4: scons build Signed-off-by: Rob Clark <[email protected]> Acked-by: Dylan Baker <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* nir: fix per_vertex_output intrinsicRob Clark2018-03-271-1/+1
| | | | | | | | | This is supposed to have both BASE and COMPONENT but num_indices was inadvertantly set to 1. Cc: <[email protected]> Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* glsl_types: fix build break with intel/msvc compilerRob Clark2018-03-271-83/+24
| | | | | | | | | | | | | | | | | | | | The VECN() macro was taking advantage of a GCC specific feature that is not available on lesser compilers, mostly for the purposes of avoiding a macro that encoded a return statement. But as suggested by Ian, we could just have the macro produce the entire method body and avoid the need for this. So let's do that instead. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105740 Fixes: f407edf3407396379e16b0be74b8d3b85d2ad7f0 Cc: Emil Velikov <[email protected]> Cc: Timothy Arceri <[email protected]> Cc: Roland Scheidegger <[email protected]> Cc: Ian Romanick <[email protected]> Signed-off-by: Rob Clark <[email protected]> Acked-by: Timothy Arceri <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: add GL_HALF_FLOAT as supported type to readpixelsLin Johnson2018-03-271-0/+2
| | | | | | | | | | | | | | | | | | | EXT_color_buffer_float spec states: "An INVALID_OPERATION error is generated ... if the color buffer is a floating-point format and type is not FLOAT, HALF FLOAT, or UNSIGNED_INT_10F_11F_11F_REV." This means that GL_HALF_FLOAT type should be supported when color buffer has floating-point format. Fixes Android CTS test android.view.cts.PixelCopyTest. v2: remove comments of EXT_color_buffer_half_float as EXT_color_buffer_float can use type GL_HALF_FLOAT Signed-off-by: Lin Johnson <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 16:53:29 +0000