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* radeonsi: reduce overhead for resident textures which need color decompressionSamuel Pitoiset2017-06-184-34/+58
| | | | | | | | | This is done by introducing a separate list. si_decompress_textures() is now 5x faster. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: reduce overhead for resident textures which need depth decompressionSamuel Pitoiset2017-06-184-8/+29
| | | | | | | This is done by introducing a separate list. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: use util_dynarray_foreach for bindless resourcesSamuel Pitoiset2017-06-182-129/+46
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/util: add util_dynarray_clear() helperSamuel Pitoiset2017-06-181-0/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: add a new HUD query for the number of resident handlesSamuel Pitoiset2017-06-184-0/+12
| | | | | | | | | Useful for debugging performance issues when ARB_bindless_texture is enabled. This query doesn't make a distinction between texture and image handles. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/gen4: Refactor depth/stencil rebaseTopi Pohjolainen2017-06-181-180/+63
| | | | | | | | Effectively there is the same code twice, once for depth and again for stencil. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965: Drop depth/stencil miptree pointers in alignment workaroundTopi Pohjolainen2017-06-182-15/+3
| | | | | | | | | In brw_workaround_depthstencil_alignment() corresponding renderbuffers are always set to refer to the same temp miptrees. There is no need to carry them in context. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen4: Simplify depth/stencil invalidate checkTopi Pohjolainen2017-06-181-13/+3
| | | | | | | There is no separate stencil on gen < 6. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen4: Remove redundant check for depth when rebasing stencilTopi Pohjolainen2017-06-181-51/+12
| | | | | | | | | | | | | In case of gen < 6 stencil (if present) is always combined with depth. Both stencil and depth attachments point to the same physical surface. Alignment workaround starts by considering depth and updates stencil accordingly. Current logic continues with stencil and in vain considers the case where depth would refer to different surface than stencil. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen4: Remove non-existing stencil and hiz buffer setupTopi Pohjolainen2017-06-182-117/+14
| | | | | | | Separate stencil and hiz are only enabled for gen6+. Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* android: ac: add missing libdrm_amdgpu shared dependencyMauro Rossi2017-06-171-0/+3
| | | | | | | | | | | | | | | | Fixes building errors in amd/common: target C: libmesa_amd_common <= external/mesa/src/amd/common/ac_gpu_info.c ... target C: libmesa_amd_common <= external/mesa/src/amd/common/ac_surface.c ... external/mesa/src/amd/common/ac_gpu_info.h:31:10: fatal error: 'amdgpu.h' file not found ^ 2 errors Fixes: 98a2492 ("ac_surface: use radeon_info from ac_gpu_info") Signed-off-by: Emil Velikov <[email protected]>
* r600: include libelf headers only as neededEmil Velikov2017-06-171-0/+2
| | | | | | | | | | | | | | | | | Headers are required only when building with OpenCL. As we're building w/o it libelf may be missing, hence we'll error out as below: src/gallium/drivers/r600/evergreen_compute.c:27:10: fatal error: 'gelf.h' file not found ^ 1 error generated. Fixes: d96a210842 ("r600g,compute: provide local copy of functions from ac_binary.c") Reviewed-by: Jan Vesely <[email protected]> Reported-by: Mauro Rossi <[email protected]> Tested-by: Mauro Rossi <[email protected]> Signed-off-by: Emil Velikov <[email protected]>
* radeonsi: include ac_binary.h for struct ac_shader_binaryEmil Velikov2017-06-171-2/+2
| | | | | | | | | | | | | | The header embeds the struct so it needs the header inclusion instead of the dummy forward declaration. Cc: Nicolai Hähnle <[email protected]> Cc: Marek Olšák <[email protected]> Cc: Tom Stellard <[email protected]> Fixes: 32206c5e560 ("radeonsi: Add radeon_shader_binary member to struct si_shader") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* r600, radeon: move radeon_shader_binary_{init,clean} back to radeonEmil Velikov2017-06-173-23/+28
| | | | | | | | | | | | | Those are used by r600 and radeonsi, so moving them within the former was a bad idea. Fixes: d96a210842b ("r600g,compute: provide local copy of functions from ac_binary.c") Cc: Jan Vesely <[email protected]> Cc: Aaron Watry <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* ac: resolve conflicts introduced with "ac: remove amdgpu.h dependency"Emil Velikov2017-06-171-1/+3
| | | | | | | | | | | | | | | | | | | The commit did not add the relevant includes - in particular stdint.h and stdbool.h for the respective standard types. At the same time, the amdgpu_device_handle typedef redeclaration was off. Fixes: 81945ded0dc ("ac: remove amdgpu.h dependency") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101471 Cc: Mark Janes <[email protected]> Cc: Gregor Münch <[email protected]> Reported-by: Bas Nieuwenhuizen <[email protected]> Reported-by: Mark Janes <[email protected]> Reported-by: Gregor Münch <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Bas Nieuwenhuizen <[email protected]>
* i965/gen4: Set depth offset when there is stencil attachment onlyTopi Pohjolainen2017-06-171-0/+6
| | | | | | | | | | | | | Current version fails to set depthstencil.depth_offset when there is only stencil attachment (it does set the intra tile offsets though). Fixes piglits: g45,g965,ilk: depthstencil-render-miplevels 1024 s=z24_s8 g45,ilk: depthstencil-render-miplevels 273 s=z24_s8 CC: [email protected] Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Remove dead code in hiz surface setupTopi Pohjolainen2017-06-171-7/+6
| | | | | | | | | In intel_hiz_miptree_buf_create() the miptree is unconditionally created with MIPTREE_LAYOUT_FORCE_ALL_SLICE_AT_LOD. Reviewed-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* intel/isl/gen6: Allow arrayed stencilTopi Pohjolainen2017-06-171-1/+0
| | | | | | | | Nothing prevents arrayed stencil surfaces even though hardware doesn't support mipmapping. Reviewed-by: Nanley Chery <[email protected]> Signed-off-by: Topi Pohjolainen <[email protected]>
* svga: add new num-failed-allocations HUD queryBrian Paul2017-06-165-2/+26
| | | | | | | This counter is incremented if we fail to allocate memory for vertex/index/const buffers, textures, etc. Reviewed-by: Neha Bhende <[email protected]>
* gallium/hud: support GALLIUM_HUD_DUMP_DIR feature on WindowsBrian Paul2017-06-161-6/+30
| | | | | | | Use a dummy implementation of the access() function. Use \ path separator. Add a few comments. Reviewed-by: Neha Bhende <[email protected]>
* svga: add a few minor commentsBrian Paul2017-06-162-1/+6
| | | | Trivial.
* mesa: whitespace fixes in enable.cBrian Paul2017-06-161-68/+68
| | | | Remove trailing whitespace, replace tabs w/ spaces, etc. Trivial.
* i965: Convert SF_STATE to genxml.Rafael Antognolli2017-06-165-288/+83
| | | | | | | | This patch finishes the work done by Ken of converting SF_STATE to genxml, and merges it with gen6+ code for emitting that state. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: The viewport state offset is actually an address.Rafael Antognolli2017-06-161-1/+1
| | | | | | | This fixes code generation on gen45. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename fields to match gen6+.Rafael Antognolli2017-06-163-3/+3
| | | | | | | "Anti-aliasing Enable" to "Anti-Aliasing Enable". Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* genxml: Rename SF_STATE field to match gen6+.Rafael Antognolli2017-06-163-9/+9
| | | | | | | | | Rename "Use Point Width State" to "Point Width Source". It accepts the same values and has the same meaning as gen6+, so lets keep them with the same name to simplify the code. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965: aa_line_distance_mode should be before the padding.Rafael Antognolli2017-06-161-1/+1
| | | | | | | It seems that it was never set correctly. Signed-off-by: Rafael Antognolli <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* swr/rast: Fix read-back of viewport array indexTim Rowley2017-06-1610-117/+182
| | | | | | | Binner/clipper read viewport array index from the vertex header as needed. Move viewport state to BACKEND_STATE. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Refactor includes to limit simdintrin.h usageTim Rowley2017-06-1616-1079/+1147
| | | | | | | Reduces the files rebuilt after modifying simdintrin.h from 84 to 64. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix read-back of render target array indexTim Rowley2017-06-165-13/+18
| | | | | | | | The last FE stage can emit render target array index. Currently we only check to see if GS is emitting it. Moved the state to BACKEND_STATE and plumbed the driver to set it. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Adjust cast for gcc warningTim Rowley2017-06-161-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Don't transition hottile resolved->dirty during store tilesTim Rowley2017-06-161-1/+4
| | | | | | Fixes crash when dumping render targets and RT surface has been deleted. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: gen_llvm_types.py support for SIMD256/SIMD512Tim Rowley2017-06-161-6/+6
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Properly size GS stage scratch spaceTim Rowley2017-06-161-1/+1
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix early z / query interactionTim Rowley2017-06-161-0/+4
| | | | | | | | | | | | | | | | For certain cases, we perform early z for optimization. The GL_SAMPLES_PASSED query was providing erroneous results because we were counting the number of samples passed before the fragment shader, which did not work if the fragment shader contained a discard. Account properly for discard and early z, by anding the zpass mask with the post fragment shader active mask, after the fragment shader. Fixes the following piglit tests: - occlusion-query-discard - occlusion_query_meta_fragments Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Share vertex memory between VS input/outputTim Rowley2017-06-161-5/+2
| | | | | | | | Removes large simdvertex stack allocation. Vertex shader must ensure reads happen before writes. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add support for dynamic vertex size for VS outputTim Rowley2017-06-163-15/+23
| | | | | | | | Add support for dynamic vertex size for the vertex shader output. Add new state in SWR_FRONTEND_STATE to specify the size. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: SIMD16 FE - improve calcDeterminantIntVerticalTim Rowley2017-06-161-12/+20
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Add support to PA for variable sized verticesTim Rowley2017-06-164-26/+38
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Rework attribute layoutTim Rowley2017-06-164-66/+103
| | | | | | | Move fixed attributes to the top and pack single component SGVs. WIP to support dynamically allocated vertex size. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Remove explicit primitive id slot in the vertex layoutTim Rowley2017-06-167-58/+33
| | | | | | | | - Remove any special casing in the PS stage when primitive ID is input. Treat as a normal attribute that must be set up properly in the FE linkage. - Remove primitive id from the PS_CONTEXT and TRI_FLAGS Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Fix invalid 16-bit format traits for A1R5G5B5Tim Rowley2017-06-161-100/+48
| | | | | | | Correctly handle formats of <= 16 bits where the component bits don't add up to the pixel size. Reviewed-by: Bruce Cherniak <[email protected]>
* swr/rast: Implement JIT shader caching to diskTim Rowley2017-06-1610-18/+358
| | | | | | Disabled by default; currently doesn't cache shaders (fs,gs,vs). Reviewed-by: Bruce Cherniak <[email protected]>
* gallium/docs: improve docs for SAMPLE_POS, SAMPLE_INFO, TXQS, MSAA semanticsBrian Paul2017-06-161-11/+47
| | | | | | | | | | | | | | | | | | | | | For the SAMPLE_POS and SAMPLE_INFO opcodes, clarify resource vs. render target queries, range of postion values, swizzling, etc. We basically follow the DX10.1 conventions. For the TXQS opcode and TGSI_SEMANTIC_SAMPLEID, clarify return value and type. For the TGSI_SEMANTIC_SAMPLEPOS system value, clarify the range of positions returned. v2: use 'undef' for unused vector components. Use (0.5, 0.5, undef, undef) for sample pos when MSAA not applicable. v3: Add note that OPCODE_SAMPLE_INFO, OPCODE_SAMPLE_POS are not used yet and the information is subject to change. Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* svga: add some missing SVGA_STATS_* enum values, prefix stringsBrian Paul2017-06-161-2/+15
| | | | | | | To fix the build when VMX86_STATS is defined. Also, some minor whitespace changes to match upstream code. Reviewed-by: Charmaine Lee <[email protected]>
* radeonsi: add new polaris12 pci idAlex Deucher2017-06-161-0/+1
| | | | | | Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: 17.0 17.1 <[email protected]>
* swr: Don't crash when encountering a VBO with stride = 0.Bruce Cherniak2017-06-161-7/+18
| | | | | | | | | | | | | | | | | | | | The swr driver uses vertex_buffer->stride to determine the number of elements in a VBO. A recent change to the state-tracker made it possible for VBO's with stride=0. This resulted in a divide by zero crash in the driver. The solution is to use the pre-calculated vertex element stream_pitch in this case. This patch fixes the crash in a number of piglit and VTK tests introduced by 17f776c27be266f2. There are several VTK tests that still crash and need proper handling of vertex_buffer_index. This will come in a follow-on patch. v2: Correctly update all parameters for VBO constants (stride = 0). Also fixes the remaining crashes/regressions that v1 did not address, without touching vertex_buffer_index. Reviewed-by: Tim Rowley <[email protected]>
* intel/isl: Add the maximum surface size limitAnuj Phogat2017-06-161-0/+22
| | | | | | | | V2: Use 2^31 bytes (2GB) surface size limit on pre-gen9 and 2^38 bytes for gen9+. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* intel/isl: Use uint64_t to store total surface sizeAnuj Phogat2017-06-162-2/+3
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Nanley Chery <[email protected]>
* i965: Mark freshly allocate bo as idleChris Wilson2017-06-161-0/+1
| | | | | | | | | | When created, buffers are idle, so mark them as such to save an early ioctl or mistakenly assuming the fresh buffer is busy. Signed-off-by: Chris Wilson <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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