summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* radeonsi: implement ARB_shader_group_voteNicolai Hähnle2017-03-314-2/+87
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: enable ARB_shader_clockNicolai Hähnle2017-03-313-2/+3
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: emit TGSI_OPCODE_CLOCKNicolai Hähnle2017-03-311-0/+21
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: implement ARB_shader_clockNicolai Hähnle2017-03-312-1/+11
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* tgsi: add CLOCK opcodeIlia Mirkin2017-03-313-2/+16
| | | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium: add PIPE_CAP_TGSI CLOCKNicolai Hähnle2017-03-3117-0/+17
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* glsl: fix clockARB builtin functionNicolai Hähnle2017-03-311-1/+1
| | | | | | | The underlying intrinsic is defined to always have a uvec2 return type. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* anv: change BLOCK_POOL_MEMFD_SIZE to 1GBTapani Pälli2017-03-311-2/+2
| | | | | | | | This allows us to run 32bit Vulkan apps on Android, ftruncate call would fail on 2GB (max size being 2GB - 1). Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* android: add libmesa_genxml as dep to libmesa_islTapani Pälli2017-03-311-1/+2
| | | | | | | | | This is to fix following compile error with libmesa_isl: mesa/src/intel/isl/isl.c:28:10: fatal error: 'genxml/genX_bits.h' file not found Fixes: f0eaf38 ("genxml: New generated header genX_bits.h (v6)") Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Emli Velikov <[email protected]>
* mesa: remove MESA_GLSL=optTimothy Arceri2017-03-314-11/+8
| | | | | | | | | This is unused. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: remove MESA_GLSL=no_opts env optionTimothy Arceri2017-03-315-16/+9
| | | | | | | | | | | | This is confusing because is only applys to GL_ARB_vertex/fragment_program, and because of that its also not very useful. If someone requires this for debugging they can just make an ad-hoc code change. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa: move FLUSH_VERTICES() call to metaTimothy Arceri2017-03-313-15/+13
| | | | | | | | There is no need for this to be in the common code. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/vbo: remove redundant _mesa_is_bufferobj() callsTimothy Arceri2017-03-311-10/+4
| | | | | | | | | This is already called inside the vbo_exec_vtx_{unmap,map}() functions. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/glthread: add async support to ARB_gpu_shader_int64 uniform functionsTimothy Arceri2017-03-311-16/+16
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa/glthread: add async support to ARB_gpu_shader_fp64 uniform functionsTimothy Arceri2017-03-311-13/+13
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* aubinator: enable snb/ilk through --genLionel Landwerlin2017-03-311-0/+2
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* intel: genxml: compress all gen files into oneLionel Landwerlin2017-03-315-62/+58
| | | | | | | | | | | | | Combining all the files into a single string didn't make any difference in the size of the aubinator binary. With this change we now also embed gen4/4.5/5 descriptions, which increases the aubinator size by ~16Kb. v2 (Lionel): rebase makefiles Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* radv: Use the guard band.Bas Nieuwenhuizen2017-03-303-13/+90
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Prepare for not using the guard band for lines & points.Bas Nieuwenhuizen2017-03-303-0/+32
| | | | | | | | | | | Vulkan Clipping is defined in terms of vertices, the scissor based clipping happens on pixels. There is a difference with points and lines, as a vertex can be outside the viewport while some pixels are in. On Vulkan thoise pixels shouldn't be drawn, while they would be with the guardband. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Drop the default viewport when 0 viewports are given.Bas Nieuwenhuizen2017-03-301-17/+2
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Set proper viewport & scissor for meta draws.Bas Nieuwenhuizen2017-03-306-75/+214
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* mesa: Fix trailing whitespace in polygon.cLyude2017-03-301-3/+3
| | | | | Signed-off-by: Lyude <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: Fix gross indenting in _mesa_PolygonMode()Lyude2017-03-301-5/+4
| | | | | Signed-off-by: Lyude <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* r300: Fix indenting in r300_get_param()Lyude2017-03-301-3/+3
| | | | | | Signed-off-by: Lyude <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* vc4: Fix indenting in vc4_screen_get_param()Lyude2017-03-301-3/+3
| | | | | | Signed-off-by: Lyude <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* intel: Add INTEL_CFLAGS to aubinator CFLAGS.Kenneth Graunke2017-03-301-1/+2
| | | | It still needs intel_aub.h. Fixes the build.
* nir: Add support for 8 and 16-bit typesJason Ekstrand2017-03-303-2/+24
| | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir/constant_expressions: Don't switch on bit size when not neededJason Ekstrand2017-03-301-14/+23
| | | | | | | | | | | | For opcodes such as the nir_op_pack_64_2x32 for which all sources and destinations have explicit sizes, the bit_size parameter to the evaluate function is pointless and *should* do nothing. Previously, we were always switching on the bit_size and asserting if it isn't one of the sizes in the list. This generates way more code than needed and is a bit cruel because it doesn't let us have a bit_size of zero on an ALU op which shouldn't need a bit_size. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir/constant_expressions: Pull the guts out into a helper blockJason Ekstrand2017-03-301-98/+101
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965: Stop using legacy dri_bufmgr_* and intel_* names.Kenneth Graunke2017-03-3010-14/+18
| | | | | | | | Eric renamed these from dri_bufmgr_* and intel_bufmgr_* to drm_intel_* in libdrm commit 4b9826408f65976a1a13387beda748b65e03ec52, circa 2008, but we've been using the legacy names this whole time. Reviewed-by: Jason Ekstrand <[email protected]>
* intel: automake: move INTEL_CFLAGS as applicableEmil Velikov2017-03-302-1/+1
| | | | | | | | | | Only common/decoder.[ch] requires it [for intel_aub.h]. v2: The code was moved to from intel/tools to intel/common, update accordingly. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* intel: android: remove libdrm_intel requirementEmil Velikov2017-03-303-12/+6
| | | | | | | | The only part which requires libdrm_intel tools/aubinator is not built on Android. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* Partially revert "amd/addrlib: silence warnings" to fix builds with DEBUGMarek Olšák2017-03-303-6/+6
| | | | This partially reverts commit 8a74140a21fe6b0d2e8a60b065b890f797f2db51.
* ddebug: implement clear_textureMarek Olšák2017-03-302-0/+34
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: fix an unused-variable warning in a release buildMarek Olšák2017-03-301-3/+1
|
* vdpau: fix a maybe-uninitialized warningMarek Olšák2017-03-301-1/+1
|
* softpipe: fix a maybe-uninitialized warningMarek Olšák2017-03-301-1/+1
| | | | | | /home/marek/dev/mesa-main/src/gallium/drivers/softpipe/sp_compute.c:178: warning: 'grid_size' may be used uninitialized in this function [-Wmaybe-uninitialized]
* gallivm: fix a maybe-uninitialized warningMarek Olšák2017-03-301-1/+1
| | | | | | | /home/marek/dev/mesa-main/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c:3598: warning: 'level' may be used uninitialized in this function [-Wmaybe-uninitialized] out1 = lp_build_cmp(&leveli_bld, PIPE_FUNC_GREATER, level, last_level); ^
* gallium/radeon: s/dcc_disable/disable_dcc/Marek Olšák2017-03-304-9/+9
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: handle incompatible DCC formats in resource_copy_regionMarek Olšák2017-03-301-0/+5
| | | | | | | Required because of later commits. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]>
* radeonsi: remove a workaround for inexact *8_SNORM blitsMarek Olšák2017-03-301-3/+1
| | | | | | | | All tests pass on Fiji now. This prevents DCC disablement due to incompatible DCC formats due to the fallback. Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]>
* gallium/radeon: add and use a new helper vi_dcc_enabledMarek Olšák2017-03-305-14/+16
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/radeon: formalize that r600_query_hw_add_result doesn't need a contextMarek Olšák2017-03-303-8/+9
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radeonsi: don't make a copy of pipe_index_buffer in draw_vboMarek Olšák2017-03-301-32/+27
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* gallium/util: use const in u_index_modify helpersMarek Olšák2017-03-302-6/+6
| | | | | | Reviewed-by: Nicolai Hähnle <[email protected]> Tested-by: Edmondo Tommasina <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* winsys/amdgpu: remove AMDGPU_INFO_NUM_EVICTIONSSamuel Pitoiset2017-03-301-4/+0
| | | | | | | | This is now exposed with libdrm_amdgpu 2.4.76. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: add Vega10 PCI IDsMarek Olšák2017-03-301-0/+8
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeon/uvd: set correct vega10 db pitch alignmentBoyuan Zhang2017-03-301-4/+12
| | | | | | | | Create new function to get correct alignment based on Asics, and change the corresponding decode message buffer and dpb buffer size calculations Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: add vce support for firmware 53.19.4Leo Liu2017-03-301-0/+6
| | | | | | | v2: squashed with other similar commits Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/vce: adapt gfx9 surface to vceLeo Liu2017-03-302-15/+51
| | | | | | Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-18 16:32:03 +0000