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* i965/gen9: use an unreserved surface alignment valueNanley Chery2015-07-011-4/+4
| | | | | | | | | | | Although the horizontal and vertical alignment fields are ignored here, 0 is a reserved value for them and may cause undefined behavior. Change the default value to an abitrary valid one. v2: add comment about chosen value (Topi). Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* i965/fs: Use the builder directly for the gen6 interpolation add(32)Jason Ekstrand2015-07-011-6/+5
| | | | | | | Now that we can create builders with a bigger width than their parent as long as it's exec_all, we don't need to create the instruction manually. Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Relax fs_builder channel group assertion when force_writemask_all ↵Francisco Jerez2015-07-013-7/+7
| | | | | | | | | | | | | | | | | | | is on. This assertion was meant to catch code inadvertently escaping the control flow jail determined by the group of channel enable signals selected by some caller, however it seems useful to be able to increase the default execution size as long as force_writemask_all is enabled, because force_writemask_all is an explicit indication that there is no longer a one-to-one correspondence between channels and SIMD components so the restriction doesn't apply. In addition reorder the calls to fs_builder::group and ::exec_all in a couple of places to make sure that we don't temporarily break this invariant in the future for instructions with exec_size higher than the dispatch width. Reviewed-by: Jason Ekstrand <[email protected]>
* nouveau: rename var name for nouveau_vieux to avoid conflict with nouveauIlia Mirkin2015-07-012-3/+3
| | | | | | | | | | | | We want to require different versions for nouveau and nouveau_vieux. autoconf will only check for NOUVEAU once if both drivers are enabled, meaning both version checks don't get executed. Rename the nouveau_vieux one to NVVIEUX to avoid the issue. Signed-off-by: Ilia Mirkin <[email protected]> Tested-by: Alexandre Courbot <[email protected]> Tested-by: Martin Peres <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* glsl: create program resource list after LinkShaderTapani Pälli2015-07-012-4/+2
| | | | | | | | | Resource list can be created properly only after LinkShader hook has been called to make sure all dead variables have been removed. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=90925
* glsl: expose build_program_resource_list functionTapani Pälli2015-07-012-1/+5
| | | | | | | | This is required so that we can move resource list creation to happen later. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* glsl: build stageref mask using IR, not symbol tableTapani Pälli2015-07-011-3/+11
| | | | | | | | | Instead of using symbol table, build mask by inspecting IR. This change is required by further patches to move resource list creation to happen later when symbol table does not exist anymore. Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Martin Peres <[email protected]>
* ilo: remove ilo_image_paramsChia-I Wu2015-07-011-75/+47
| | | | It suffices to use ilo_image_layout directly.
* ilo: add image_init_gen6_transfer_layout()Chia-I Wu2015-07-011-75/+37
| | | | It replaces img_init_for_transfer().
* ilo: add image_set_gen6_bo_size()Chia-I Wu2015-07-013-118/+89
| | | | It replaces img_calculate_bo_size().
* ilo: add image_set_gen6_{hiz,mcs}Chia-I Wu2015-07-011-49/+61
| | | | They replace img_calculate_{hiz,mcs}_size().
* ilo: add image_get_gen6_monolithic_size()Chia-I Wu2015-07-011-67/+67
| | | | It replaces img_align().
* ilo: add image_get_gen6_lods()Chia-I Wu2015-07-011-88/+148
| | | | It replaces img_init_lods() and img_init_layer_height().
* ilo: add image_get_gen{6,7}_alignment()Chia-I Wu2015-07-011-159/+177
| | | | They replace img_init_alignments().
* ilo: add image_get_gen6_{hiz,mcs}_enable()Chia-I Wu2015-07-011-101/+97
| | | | They replace img_init_aux().
* ilo: add image_get_gen6_tiling()Chia-I Wu2015-07-011-132/+177
| | | | It replaces img_init_tiling().
* ilo: add image_get_gen6_layout()Chia-I Wu2015-07-011-82/+107
| | | | It replaces only img_init_walk() right now. It will replace all img_init_*().
* nv50/ir: copy joinAt when splitting both before and afterIlia Mirkin2015-07-013-0/+5
| | | | | | | | | | | | | | | | | | | | | The current implementation only moves the joinAt when splitting after the given instruction, not before it. So if you have a BB with foo instr bar joinat and thus with joinAt set, we end up first splitting before instr, at which point the instr's bb is updated to the new bb. Since that bb doesn't have a joinAt set (despite containing one), when splitting after the instr, there is nothing to copy over. Since the joinat will be in the "split" bb irrespective of whether we're splitting before or after the instruction, move it over in either case. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91124 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* docs: update for llvmpipe fp64 supportDave Airlie2015-07-012-2/+4
| | | | Signed-off-by: Dave Airlie <[email protected]>
* gallivm: add fp64 support. (v2.1)Dave Airlie2015-07-018-31/+553
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit to llvmpipe. Two things that don't mix well are SoA and doubles, see emit_fetch_double, and emit_store_double_chan in this. I've also had to split emit_data.chan, to add src_chan, which can be different for doubles. It handles indirect double fetches from temps, inputs, constants and immediates. It doesn't handle double stores to indirects, however it appears the mesa/st doesn't currently emit these, it always does UARL/MOV combos, which will work fine. tested with piglit, no regressions, all the fp64 tests seem to pass. v2: switch to using shuffles for fetch/store (Roland) assert on indirect double stores - mesa/st never emits these (it uses MOV) fix indirect temp/input/constant/immediates (Roland) typos/formatting fixes (Roland) v2.1: cleanup some long lines, emit_store_double_chan cleanups. Reviewed-by: Roland Scheidegger <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* tgsi: add infer support for double opcodes.Dave Airlie2015-07-011-0/+37
| | | | | Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* freedreno: use consistent version string formatTimothy Arceri2015-07-011-1/+1
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* glsl: use consistent version string formatTimothy Arceri2015-07-011-7/+7
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* i965/fs: Fix PIXEL_X/Y in regs_read()Jason Ekstrand2015-06-301-1/+1
| | | | PIXEL_X/Y takes a vec2 in the first argument
* i965/fs: Remove the width field from fs_regJason Ekstrand2015-06-308-107/+30
| | | | | | | | | | | | | As of now, the width field is no longer used for anything. The width field "seemed like a good idea at the time" but is actually entirely redundant with the instruction's execution size. Initially, it gave us the ability to easily set the instructions execution size based entirely on register widths. With the builder, we can easiliy set the sizes explicitly and the width field doesn't have as much purpose. At this point, it's just redundant information that can get out of sync so it really needs to go. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs_generator: Use inst->exec_size for determining hardware reg widthsJason Ekstrand2015-06-301-7/+7
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Use exec_size instead of dst.width for computing component sizeJason Ekstrand2015-06-305-8/+8
| | | | | | | | There are a variety of places where we use dst.width / 8 to compute the size of a single logical channel. Instead, we should be using exec_size. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Use the builder dispatch_width for computing register offsetsJason Ekstrand2015-06-301-1/+1
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Use the builder dispatch width instead of dst.width for pull constantsJason Ekstrand2015-06-301-4/+4
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Remove exec_size guessing from fs_inst::init()Jason Ekstrand2015-06-301-22/+0
| | | | | | | | Now that all of the non-explicit constructors are gone, we don't need to guess anymore. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs_builder: Use the dispatch width for setting exec sizesJason Ekstrand2015-06-301-9/+11
| | | | | | | Previously we used dst.width but the two *should* be the same. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Use exec_size for determining regs read/written and partial writesJason Ekstrand2015-06-301-3/+3
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Remove fs_inst constructors that don't take an explicit exec_sizeJason Ekstrand2015-06-304-39/+8
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Make better use of the builder in shader_timeJason Ekstrand2015-06-301-6/+8
| | | | | | | | | Previously, we were just depending on register widths to ensure that various things were exec_size of 1 etc. Now, we do so explicitly using the builder. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Add a builder argument to offset()Jason Ekstrand2015-06-307-123/+132
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Move offset(fs_reg, unsigned) to brw_fs.hJason Ekstrand2015-06-302-21/+21
| | | | | | | | Shortly, offset() will depend on the builder so we need it moved to some place where it has access to that. Reviewed-by: Iago Toral Quiroga <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/blorp: Explicitly set execution sizes for new'd instructionsJason Ekstrand2015-06-301-4/+5
| | | | | | | | This doesn't affect instructions allocated using the builder. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Set the builder group for emitting FB-write stencil/AA alphaJason Ekstrand2015-06-301-1/+1
| | | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Explicitly set the exec_size on the add(32) in interpolation setupJason Ekstrand2015-06-301-4/+6
| | | | | | | | | | | | | | | | | Soon we will start using the builder to explicitly set all the execution sizes. We could make a 32-wide builder, but the builder asserts that we never grow it which is usually a reasonable assumption. Since this one instruction is a bit of an odd-ball, we just set the exec_size explicitly. v2: Explicitly new the fs_inst instead of using the builder and setting exec_size after the fact. v3: Set force_writemask_all with the builder instead of directly. The builder over-writes it if we set it manually. Also, if we don't have force_writemask_all in the builder it will assert-fail on SIMD32. Reviewed-by: Iago Toral Quiroga <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Properly handle LOAD_PAYLOAD in fs_inst::regs_readJason Ekstrand2015-06-301-0/+5
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Report the right value in fs_inst::regs_read() for PIXEL_X/YJason Ekstrand2015-06-301-2/+9
| | | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Fix fs_inst::regs_read() for uniform pull constant loadsJason Ekstrand2015-06-301-0/+6
| | | | | | | | | | | | Previously, fs_inst::regs_read() fell back to depending on the register width for the second source. This isn't really correct since it isn't a SIMD8 value at all, but a SIMD4x2 value. This commit changes it to explicitly be always one register. v2: Use mlen for determining the number of registers read Reviewed-by: Iago Toral Quiroga <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Actually set/use the mlen for gen7 uniform pull constant loadsJason Ekstrand2015-06-302-13/+15
| | | | | | | | | Previously, we were allocating the payload with different sizes per gen and then figuring out the mlen in the generator based on gen. This meant, among other things, that the higher level passes knew nothing about it. Acked-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use a switch statement in fs_inst::regs_read()Jason Ekstrand2015-06-301-22/+23
| | | | | | | | This makes things a little simpler, more efficient, and quite a bit more readable. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* nir: remove parent_instr from nir_registerConnor Abbott2015-06-303-17/+0
| | | | | | It's no longer used. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: remove nir_src_get_parent_instr()Connor Abbott2015-06-301-10/+0
| | | | | | It's now unused. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: emit constants only onceConnor Abbott2015-06-302-13/+16
| | | | | | | | | | | | | | | | | | | Before, we would lazily emit a MOV whenever we encountered a use of a constant. Now that we have a dedicated file for SSA values, we can instead only emit the MOV's once, which is more consistent and prevents us from relying on CSE to re-combine the constants when they aren't absorbed into the instruction. total instructions in shared programs: 6078991 -> 6073118 (-0.10%) instructions in affected programs: 402221 -> 396348 (-1.46%) helped: 1527 HURT: 0 GAINED: 8 LOST: 2 v2: split this out from the previous commit (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: use SSA values directlyConnor Abbott2015-06-305-30/+52
| | | | | | | | | | | Before, we would use registers, but set a magical "parent_instr" field to indicate that it was actually purely an SSA value (i.e., it wasn't involved in any phi nodes). Instead, just use SSA values directly, which lets us get rid of the hack and reduces memory usage since we're not allocating a nir_register for every value. It also makes our handling of load_const more consistent compared to the other instructions. Reviewed-by: Jason Ekstrand <[email protected]>
* nir/from_ssa: add a flag to not convert everything from SSAConnor Abbott2015-06-304-10/+26
| | | | | | | | | | | | | We already don't convert constants out of SSA, and in our backend we'd like to have only one way of saying something is still in SSA. The one tricky part about this is that we may now leave some undef instructions around if they aren't part of a phi-web, so we have to be more careful about deleting them. v2: rename and flip meaning of flag (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* egl/x11: handle when invalid drawable is passed in create_surfaceEmil Velikov2015-06-301-0/+4
| | | | | | | | | 0 is not used as a valid drawable id, as such there is no point in attempting to query its geometry. Just bail out early and provide the more meaningful EGL_BAD_NATIVE_WINDOW to the user. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
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