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* i965/fs: Remove exec_size guessing from fs_inst::init()Jason Ekstrand2015-06-301-22/+0
| | | | | | | | Now that all of the non-explicit constructors are gone, we don't need to guess anymore. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs_builder: Use the dispatch width for setting exec sizesJason Ekstrand2015-06-301-9/+11
| | | | | | | Previously we used dst.width but the two *should* be the same. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Use exec_size for determining regs read/written and partial writesJason Ekstrand2015-06-301-3/+3
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Remove fs_inst constructors that don't take an explicit exec_sizeJason Ekstrand2015-06-304-39/+8
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Make better use of the builder in shader_timeJason Ekstrand2015-06-301-6/+8
| | | | | | | | | Previously, we were just depending on register widths to ensure that various things were exec_size of 1 etc. Now, we do so explicitly using the builder. Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Add a builder argument to offset()Jason Ekstrand2015-06-307-123/+132
| | | | | Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Move offset(fs_reg, unsigned) to brw_fs.hJason Ekstrand2015-06-302-21/+21
| | | | | | | | Shortly, offset() will depend on the builder so we need it moved to some place where it has access to that. Reviewed-by: Iago Toral Quiroga <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/blorp: Explicitly set execution sizes for new'd instructionsJason Ekstrand2015-06-301-4/+5
| | | | | | | | This doesn't affect instructions allocated using the builder. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Set the builder group for emitting FB-write stencil/AA alphaJason Ekstrand2015-06-301-1/+1
| | | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Explicitly set the exec_size on the add(32) in interpolation setupJason Ekstrand2015-06-301-4/+6
| | | | | | | | | | | | | | | | | Soon we will start using the builder to explicitly set all the execution sizes. We could make a 32-wide builder, but the builder asserts that we never grow it which is usually a reasonable assumption. Since this one instruction is a bit of an odd-ball, we just set the exec_size explicitly. v2: Explicitly new the fs_inst instead of using the builder and setting exec_size after the fact. v3: Set force_writemask_all with the builder instead of directly. The builder over-writes it if we set it manually. Also, if we don't have force_writemask_all in the builder it will assert-fail on SIMD32. Reviewed-by: Iago Toral Quiroga <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Properly handle LOAD_PAYLOAD in fs_inst::regs_readJason Ekstrand2015-06-301-0/+5
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Report the right value in fs_inst::regs_read() for PIXEL_X/YJason Ekstrand2015-06-301-2/+9
| | | | | | Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Fix fs_inst::regs_read() for uniform pull constant loadsJason Ekstrand2015-06-301-0/+6
| | | | | | | | | | | | Previously, fs_inst::regs_read() fell back to depending on the register width for the second source. This isn't really correct since it isn't a SIMD8 value at all, but a SIMD4x2 value. This commit changes it to explicitly be always one register. v2: Use mlen for determining the number of registers read Reviewed-by: Iago Toral Quiroga <[email protected]> Acked-by: Francisco Jerez <[email protected]>
* i965/fs: Actually set/use the mlen for gen7 uniform pull constant loadsJason Ekstrand2015-06-302-13/+15
| | | | | | | | | Previously, we were allocating the payload with different sizes per gen and then figuring out the mlen in the generator based on gen. This meant, among other things, that the higher level passes knew nothing about it. Acked-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Use a switch statement in fs_inst::regs_read()Jason Ekstrand2015-06-301-22/+23
| | | | | | | | This makes things a little simpler, more efficient, and quite a bit more readable. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* nir: remove parent_instr from nir_registerConnor Abbott2015-06-303-17/+0
| | | | | | It's no longer used. Reviewed-by: Jason Ekstrand <[email protected]>
* nir: remove nir_src_get_parent_instr()Connor Abbott2015-06-301-10/+0
| | | | | | It's now unused. Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: emit constants only onceConnor Abbott2015-06-302-13/+16
| | | | | | | | | | | | | | | | | | | Before, we would lazily emit a MOV whenever we encountered a use of a constant. Now that we have a dedicated file for SSA values, we can instead only emit the MOV's once, which is more consistent and prevents us from relying on CSE to re-combine the constants when they aren't absorbed into the instruction. total instructions in shared programs: 6078991 -> 6073118 (-0.10%) instructions in affected programs: 402221 -> 396348 (-1.46%) helped: 1527 HURT: 0 GAINED: 8 LOST: 2 v2: split this out from the previous commit (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* i965/fs: use SSA values directlyConnor Abbott2015-06-305-30/+52
| | | | | | | | | | | Before, we would use registers, but set a magical "parent_instr" field to indicate that it was actually purely an SSA value (i.e., it wasn't involved in any phi nodes). Instead, just use SSA values directly, which lets us get rid of the hack and reduces memory usage since we're not allocating a nir_register for every value. It also makes our handling of load_const more consistent compared to the other instructions. Reviewed-by: Jason Ekstrand <[email protected]>
* nir/from_ssa: add a flag to not convert everything from SSAConnor Abbott2015-06-304-10/+26
| | | | | | | | | | | | | We already don't convert constants out of SSA, and in our backend we'd like to have only one way of saying something is still in SSA. The one tricky part about this is that we may now leave some undef instructions around if they aren't part of a phi-web, so we have to be more careful about deleting them. v2: rename and flip meaning of flag (Jason) Reviewed-by: Jason Ekstrand <[email protected]>
* egl/x11: handle when invalid drawable is passed in create_surfaceEmil Velikov2015-06-301-0/+4
| | | | | | | | | 0 is not used as a valid drawable id, as such there is no point in attempting to query its geometry. Just bail out early and provide the more meaningful EGL_BAD_NATIVE_WINDOW to the user. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* egl/wayland: cleanup dri2_wl_create_surface error pathEmil Velikov2015-06-301-3/+1
| | | | | Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* egl/wayland: handle NULL native_window in create_surfaceEmil Velikov2015-06-301-0/+5
| | | | | | | | | Raise EGL_BAD_NATIVE_WINDOW instead of crashing. v2: s/Rise/Raise/ (spotted by Michel) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* egl/drm: plug memory leakEmil Velikov2015-06-301-2/+5
| | | | | | | | | Free the memory for dri2_surf in the unlikely case that one provides NULL for native_window. Also set the relevant EGL_ERROR to provide feedback to the user. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* gallium/ttn: don't upset nir_validate w/ BRK'sRob Clark2015-06-301-1/+1
| | | | | | | | | | | | | | Previously we were unconditionally doing ttn_get_src() even for instructions with no src's. Which created a lot of unnecessary load_const instructions. These were mostly harmless since NIR opt passes would strip them back out. But for an ENDIF following a BRK, it would result in load_const instructions created after the NIR break instruction. Which nir_validate dislikes. But we can actually just dtrt by using NumSrcRegs instead. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: add TXB2Rob Clark2015-06-301-0/+11
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* gallium/ttn: partial fix for output arraysRob Clark2015-06-301-2/+4
| | | | | | | | | | It isn't quite yet practical to enable TGSI_ANY_INOUT_DECL_RANGE shader cap yet, at least not in drivers that need lower_to_scalar pass (which right now is all of the ttn users), since the register arrays do not get converted to SSA, which angers nir_lower_alu_to_scalar. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* nir: cleanup open-coded instruction castsRob Clark2015-06-303-3/+3
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* freedreno/ir3: cache defining instructionRob Clark2015-06-303-69/+91
| | | | | | | | | It is silly to traverse back to find first instruction that writes part of a larger "virtual" register many times per instruction (plus per use as a src to later instructions). Cache this information so we only figure it out once. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix RA issue with faninRob Clark2015-06-301-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | The fanin source could be grouped, for example with shaders like: VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], GENERIC[9] DCL SAMP[0] DCL SVIEW[0], 2D, FLOAT DCL TEMP[0], LOCAL 0: MOV TEMP[0].xy, IN[1].xyyy 1: MOV TEMP[0].w, IN[1].wwww 2: TXF TEMP[0], TEMP[0], SAMP[0], 2D 3: MOV OUT[1], TEMP[0] 4: MOV OUT[0], IN[0] 5: END The second arg to the isaml is IN[1].w, so we need to look at the fanin source to get the correct offset. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add ir3_shader_disasm()Rob Clark2015-06-303-120/+124
| | | | | | | | | Split out most of dump_info() from ir3_cmdline compiler into a function that can be used both by cmdline compiler and also for the disasm debug option. This way, for FD_MESA_DEBUG=disasm we also get to see intput/ output registers, etc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix for sparse-samplersRob Clark2015-06-301-3/+7
| | | | | | | | | Some piglit tests, like arb_fragment_program-sparse-samplers, result in having a null samp#0 but valid samp#1. TODO: a3xx probably needs similar fix Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix crash in fail pathRob Clark2015-06-303-3/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix crash in RARob Clark2015-06-301-2/+5
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fixes for indirect writesRob Clark2015-06-303-4/+12
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix constlen in case of load_uniform_indirectRob Clark2015-06-301-0/+5
| | | | | | | | We can't rely on what we get from the assembler if we have indirect addressing of constant file, since the assembler doesn't know the array index. This got lost in the transition to NIR. Signed-off-by: Rob Clark <[email protected]>
* glsl: validate sampler array indexing for 'constant-index-expression'Tapani Pälli2015-06-301-0/+77
| | | | | | | | | | | | | | Desktop GLSL < 130 and GLSL ES < 300 allow sampler array indexing where index can contain a loop induction variable. This extra check will warn during linking if some of the indexes could not be turned in to constant expressions. v2: warning instead of error for backends that did not enable EmitNoIndirectSampler option (have dynamic indexing) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Cc: "10.5" and "10.6" <[email protected]>
* mesa/st: use EmitNoIndirectSampler if !ARB_gpu_shader5Tapani Pälli2015-06-301-0/+5
| | | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Cc: "10.5" and "10.6" <[email protected]>
* i915: use EmitNoIndirectSamplerTapani Pälli2015-06-301-0/+3
| | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Cc: "10.5" and "10.6" <[email protected]>
* i965: use EmitNoIndirectSampler for gen < 7Tapani Pälli2015-06-301-0/+4
| | | | | | Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Cc: "10.5" and "10.6" <[email protected]>
* mesa/glsl: new compiler option EmitNoIndirectSamplerTapani Pälli2015-06-302-0/+13
| | | | | | | | | | | | | | | | Patch provides new compiler option for backend to force unroll loops that have non-constant expression indexing on sampler arrays. This makes sure that we can never end up with a shader that uses loop induction variable as sampler array index but does not unroll because of having too much instructions. This would not work without dynamic indexing support. v2: change option name as EmitNoIndirectSampler Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Cc: "10.5" and "10.6" <[email protected]>
* glsl: Allow dynamic sampler array indexing with GLSL ES < 3.00Tapani Pälli2015-06-301-18/+18
| | | | | | | | | | | | | | | | | | | | Dynamic indexing of sampler arrays is prohibited by GLSL ES 3.00. Earlier versions allow 'constant-index-expression' indexing, where index can contain a loop induction variable. Patch allows dynamic indexing for sampler arrays when GLSL ES < 3.00. This change makes 'sampler-array-index.frag' parser test in Piglit pass + fishgl.com works when running Chrome on OpenGL ES 2.0 backend v2: small change and some more commit message (Tapani) v3: refactor checks to make it more readable (Ian Romanick) v4: change warning comment in GLSL ES case (Curro) Signed-off-by: Tapani Pälli <[email protected]> Signed-off-by: Kalyan Kondapally <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Cc: "10.5" and "10.6" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84225
* nv50/ir: fix emission of address reg in 3rd sourceIlia Mirkin2015-06-301-2/+6
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91056 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.5 10.6" <[email protected]>
* i965: Don't use GCC extension for ?: with only two operands.Kenneth Graunke2015-06-291-3/+5
| | | | | | | | | | | | | | | | | | | From the "apparently I don't know C" files...GCC apparently supports: x ?: y which is equivalent to x ? x : y except that it doesn't cause side-effects to occur twice. See: https://gcc.gnu.org/onlinedocs/gcc/Conditionals.html#Conditionals This was confusing and looked like a typo. It doesn't really buy us anything, so just write the obvious code in normal C. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* egl/haiku: fix Mesa build under HaikuAlexander von Gluck IV2015-06-291-14/+14
| | | | | Performing a goto crosses the initialization of 'BWindow* win' breaking the build. We also fix a missing semicolon.
* nv30: align transfer stride to 64, required by blit, sifm transfer implsIlia Mirkin2015-06-291-2/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv30: allow vertex state creation with 0 elementsIlia Mirkin2015-06-291-2/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv30: reset fragprog bufctx at bind timeIlia Mirkin2015-06-291-1/+8
| | | | | | | | A clear will do a partial validate, which will in turn reference all the buffers in the bufctx again. However the fragprog last validated might have already been deleted. So reset the bufctx when updating state. Signed-off-by: Ilia Mirkin <[email protected]>
* nv30: modernize fp upload logicIlia Mirkin2015-06-291-10/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nv30: provide a minimum map buffer alignmentIlia Mirkin2015-06-291-1/+2
| | | | | | | Otherwise we return 0, which is out of spec. Return 64 like all the other nouveau drivers. Signed-off-by: Ilia Mirkin <[email protected]>
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