| Commit message (Collapse) | Author | Age | Files | Lines |
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Extend ilo_builder_writer_reloc() for Gen8 memory addressing. Add new
wrappers, ilo_builder_surface_reloc64(() and ilo_builder_batch_reloc64().
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Based on what we know from the classic driver.
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Accumulated changes for various renames and additions, including Gen8
definitions. Some of the dynamic state __SIZE no longer means the size of an
element, but the size of an array of elements. The changes can be seen in
ilo_render_dynamic.c.
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Add dsa_get_stencil_enable_gen6(), dsa_get_depth_enable_gen6(), and
dsa_get_alpha_enable_gen6() to be called from ilo_gpe_init_dsa().
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Make ilo_blend_state more space efficient and forward-looking.
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Use signed int for sample positions and add helpers to access them. Call them
patterns instead of positions.
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total instructions in shared programs: 5950326 -> 5949286 (-0.02%)
instructions in affected programs: 88264 -> 87224 (-1.18%)
helped: 692
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Hurts some Psychonauts shaders, but after the next patch (which this
enables) they're fewer instructions than before this patch.
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LINTERP is implemented as a PLN instruction or a LINE+MAC. PLN and MAC
can do conditional mod. CINTERP is just a MOV.
total instructions in shared programs: 5952103 -> 5950284 (-0.03%)
instructions in affected programs: 324573 -> 322754 (-0.56%)
helped: 1819
We lose the SIMD16 in one Unigine Heaven shader which appears six times
in shader-db.
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Dead since
commit 284ce20901b0c2cfab1d952cc129b8f3cd068f12
Author: Eric Anholt <eric@anholt.net>
Date: Fri Aug 20 10:52:14 2010 -0700
Remove remnants of the old glsl compiler.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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And unfortunately other shaders do the same thing but with >=/<= which
we can't apply this optimization to because of NaNs.
instructions in affected programs: 23309 -> 22938 (-1.59%)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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No change on shader-db on i965.
v2: Reword the comment due to feedback from Erik Faye-Lund
Reviewed-by: Connor Abbott <cwabbott0@gmail.com> (v1)
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> (v1)
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We want the size of a float per component, not the size of a whole vec4.
NIR instructions on i965:
total instructions in shared programs: 1261937 -> 1261929 (-0.00%)
instructions in affected programs: 114 -> 106 (-7.02%)
Looking at one of these examples (tesseract), it's from vec4 load_consts
for a MRT solid fill, which do get CSEed now that we don't memcmp off the
end of the const value and into the SSA def. For the 1-component loads
that are common in i965, we were only memcmping off into the rest of the
usually zero-filled const_value.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
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Missed in commit ca675b73, but got right in the companion commit 3c28b2c0.
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xfont.c:237:14: error: implicit declaration of function 'GetGLXDRIDrawable' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
glxdraw = GetGLXDRIDrawable(CC->currentDpy, CC->currentDrawable);
^
Fixes regression from 291be28476ea60c6fb1eb2a882e2e25def5d3735
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>
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../../../src/mesa/main/compiler.h:47:10: fatal error: 'util/macros.h' file not found
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>
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Lots of shaders divide by exp2(...) which we turn into a multiplication
by the reciprocal. We can avoid the reciprocal by simply negating exp2's
argument.
total instructions in shared programs: 5947154 -> 5946695 (-0.01%)
instructions in affected programs: 118661 -> 118202 (-0.39%)
helped: 380
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
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Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
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Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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Same as commit 3654b6d4 to the fs backend.
total instructions in shared programs: 5945788 -> 5945787 (-0.00%)
instructions in affected programs: 36 -> 35 (-2.78%)
helped: 1
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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Same as commit c4fab711 to the fs backend.
total instructions in shared programs: 5945998 -> 5945788 (-0.00%)
instructions in affected programs: 74665 -> 74455 (-0.28%)
helped: 399
HURT: 180
It hurts some programs because we make no attempts in the vec4 backend
to avoid MADs if they have constant (or vector uniform) arguments.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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Skylake+ doesn't support setting a depth buffer to a 1D surface but it
does allow pretending it's a 2D texture with a height of 1 instead.
This fixes the GL_DEPTH_COMPONENT_* tests of the copyteximage piglit
test (and also seems to avoid a subsequent GPU hang).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89037
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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non-renderbuffers.
Null surfaces are going to be useful to have something to point
unbound image units to, as the ARB_shader_image_load_store extension
requires us to behave deterministically in cases where some shader
tries to access an unbound image unit: Invalid stores and atomics are
supposed to be discarded and invalid loads are supposed to return
zero, which is precisely what the null surface does.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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v2: Bump the number of supported image uniforms to 32 (Ken).
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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It doesn't really improve locality of texture fetches, quite the
opposite it's a waste of memory bandwidth and space due to tile
alignment.
v2: Check mt->logical_height0 instead of mt->target (Ken). Add short
comment explaining why they shouldn't be tiled.
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
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It's expanded to several instructions.
Reviewed-by: Matt Turner <mattst88@gmail.com>
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Negation of UD/UW sources behaves the same as for D/W sources, taking
the two's complement of the source, except for bitwise logical
operations on Gen8 and up which take the one's complement. Fixes
crash in a GLSL shader with subtraction of two unsigned values.
Reviewed-by: Matt Turner <mattst88@gmail.com>
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Reviewed-by: Matt Turner <mattst88@gmail.com>
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In preparation for some send from GRF instructions that will require
larger payloads.
Reviewed-by: Matt Turner <mattst88@gmail.com>
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Reviewed-by: Matt Turner <mattst88@gmail.com>
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Reviewed-by: Matt Turner <mattst88@gmail.com>
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multiple registers.
v2: Avoid nested ternary operators in vec4_instruction::regs_read(). (Matt)
Reviewed-by: Matt Turner <mattst88@gmail.com>
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from GRF.
Reviewed-by: Matt Turner <mattst88@gmail.com>
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So regs_written gets initialized with a sensible value.
Reviewed-by: Matt Turner <mattst88@gmail.com>
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Reviewed-by: Matt Turner <mattst88@gmail.com>
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Reviewed-by: Matt Turner <mattst88@gmail.com>
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Scalar registers are required to have zero stride, fix the
regs_written calculation not to assume that the instruction writes
zero registers in that case.
v2: Rename CEILING() to DIV_ROUND_UP(). (Matt, Ken)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
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provided on construction.
Using 'ralloc*(this, ...)' is wrong if the object has automatic
storage or was allocated through any other means. Use normal dynamic
memory instead.
Reviewed-by: Matt Turner <mattst88@gmail.com>
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