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* i965/fs: Combine tex/fb_write operations (opt)Ben Widawsky2015-04-143-0/+103
* i965/fs: Only emit FS_OPCODE_PLACEHOLDER_HALT if there are discardsBen Widawsky2015-04-141-1/+4
* i965/fs: Create a has_side_effects for fs_instBen Widawsky2015-04-142-0/+7
* i965: replace __FUNCTION__ with __func__Marius Predut2015-04-1424-72/+72
* i915: replace __FUNCTION__ with __func__Marius Predut2015-04-1424-107/+107
* glx: replace __FUNCTION__ with __func__Marius Predut2015-04-141-2/+2
* main: replace __FUNCTION__ with __func__Marius Predut2015-04-146-10/+10
* state_tracker: replace __FUNCTION__ with __func__Marius Predut2015-04-148-18/+18
* swrast: replace __FUNCTION__ with __func__Marius Predut2015-04-145-7/+7
* vbo: replace __FUNCTION__ with __func__Marius Predut2015-04-144-5/+5
* tnl: replace __FUNCTION__ with __func__Marius Predut2015-04-148-40/+40
* i965/fs: Correct mistake in determining whether a MUL is negated.Matt Turner2015-04-141-1/+1
* i965/skl: Use an exec size of 8 to initialise the message headerNeil Roberts2015-04-142-2/+2
* i965/fs: Always invert predicate of SEL with swapped argumentsIan Romanick2015-04-141-5/+5
* radeon/llvm: Improve codegen for KILL_IFTom Stellard2015-04-141-0/+29
* radeon/llvm: Run LLVM's instruction combining passTom Stellard2015-04-141-0/+1
* radeonsi: Add header and footer to shader stat dumpTom Stellard2015-04-141-2/+4
* i965: Fix software primitive restart with indirect draws.Kenneth Graunke2015-04-141-2/+4
* i965: Implement proper workaround for Gen4 GPU CONSTANT_BUFFER hangs.Kenneth Graunke2015-04-141-13/+26
* i965: Fix INTEL_DEBUG=shader_time for SIMD8 VS.Kenneth Graunke2015-04-141-0/+3
* vc4: Add a blitter path using just the render thread.Eric Anholt2015-04-131-0/+127
* vc4: Allow submitting jobs with no bin CL in validation.Eric Anholt2015-04-134-11/+19
* vc4: Move the blit code to a separate file.Eric Anholt2015-04-134-64/+92
* vc4: Separate out a bit of code for submitting jobs to the kernel.Eric Anholt2015-04-134-90/+139
* vc4: When asked to sample from a raster texture, make a shadow tiled copy.Eric Anholt2015-04-131-2/+9
* vc4: Fix off-by-one in branch target validation.Eric Anholt2015-04-131-1/+1
* vc4: Use NIR-level lowering for idiv.Eric Anholt2015-04-131-11/+1
* vc4: Add a bunch of type conversions.Eric Anholt2015-04-131-0/+12
* st/mesa: align cube map arrays layersDave Airlie2015-04-141-1/+1
* st/mesa: convert sub image for cube map arrays to 2d arrays for uploadDave Airlie2015-04-141-0/+5
* i965: Flush batchbuffer containing the query on glQueryCounter.Mathias Froehlich2015-04-131-0/+2
* vc4: Use the blit interface for updating shadow textures.Eric Anholt2015-04-131-13/+31
* vc4: Remove dead fields from vc4_surface.Eric Anholt2015-04-131-3/+0
* vc4: Skip sending down the clear colors if not clearing.Eric Anholt2015-04-131-5/+7
* vc4: Sync with kernel changes to relax BCL versus RCL validation.Eric Anholt2015-04-131-22/+3
* vc4: Fix another space allocation mistake.Eric Anholt2015-04-131-0/+1
* vc4: Add missed accounting for the size of the semaphore.Eric Anholt2015-04-131-0/+2
* swrast: Mark MAX_GLUINT literal with u suffix.Matt Turner2015-04-131-1/+1
* i965: Don't bother freeing NULL.Matt Turner2015-04-131-4/+2
* i965: Lift some restrictions on dma_buf EGLImagesChad Versace2015-04-133-22/+7
* i965: Disable aux buffers for EGLImage-backed miptreesChad Versace2015-04-132-5/+19
* i965: Change intel_miptree_create_for_bo() signatureChad Versace2015-04-136-11/+21
* i965: Add field intel_mipmap_tree::disable_aux_buffersChad Versace2015-04-132-2/+29
* i965: Refactor brw_is_hiz_depth_format()Chad Versace2015-04-135-25/+30
* i965: Declare intel_miptree_create_layout() as staticChad Versace2015-04-132-14/+1
* i965: Declare intel_miptree_alloc_mcs() as staticChad Versace2015-04-132-6/+6
* docs: Improve LLVM_USE_CRT_xxx instructions.Jose Fonseca2015-04-131-5/+27
* glx: Include util/macros.h instead of redefining PRINTFLIKE.Jose Fonseca2015-04-131-6/+1
* util/ralloc: Fix `extern "C"` usage.Jose Fonseca2015-04-131-4/+4
* mesa: Remove pointless USE_EXTERNAL_DXTN_LIB macro.Jose Fonseca2015-04-132-9/+1
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