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* freedreno: implement fenceRob Clark2015-02-214-74/+65
| | | | | | | | | | I never actually implemented the stubbed out fence stuff back in the early days. Fix that. We'll need a few libdrm_freedreno changes to handle timeout properly, so ignore that for now to avoid a libdrm_freedreno dependency bump. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a2xx: fix increment in assertRob Clark2015-02-211-1/+2
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88883 Signed-off-by: Rob Clark <[email protected]>
* i965/fs: Use fs_reg for CS/VS atomics pixel mask immediate dataJordan Justen2015-02-211-2/+2
| | | | | | | | | | | The brw_imm_ud will yield a HW_REG which then will introduce a barrier for certain optimization opportunities. No piglit regressions seen with gen8 (simd8vs). Suggested-by: Matt Turner <[email protected]> Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Set pixel/sample mask for compute shaders atomic opsJordan Justen2015-02-211-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | For fragment programs, we pull this mask from the payload header. The same mask doesn't exist for compute shaders, so we set all bits to enabled. Previously we were setting 0xff to support SIMD8 VS, but with CS we support SIMD16, and therefore we change this to 0xffff. Related commits for SIMD8 VS: commit d9cd982d556be560af3bcbcdaf62b6b93eb934a5 Author: Ben Widawsky <[email protected]> Date: Sun Feb 15 20:06:59 2015 -0800 i965/simd8vs: Fix SIMD8 atomics commit 4a95be9772a255776309f23180519a4a8560f2dd Author: Jordan Justen <[email protected]> Date: Tue Feb 17 09:57:35 2015 -0800 i965/simd8vs: Fix SIMD8 atomics (read-only) Note: this mask is ANDed with the execution mask, so some channels may not end up issuing the atomic operation. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Ben Widawsky <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* ilo: R32G32B32_FLOAT need no special care on Gen8+Chia-I Wu2015-02-211-3/+6
| | | | | Gen8+ must use VALIGN_4. Unlike prior Gens, R32G32B32_FLOAT should supposedly support VALIGN_4.
* ilo: 128 BPP formats can use TiledY on Gen7.5+Chia-I Wu2015-02-211-1/+6
| | | | The restriction is lifted.
* nvc0: enable double supportIlia Mirkin2015-02-203-3/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: remove merge/split pairs to allow normal propagation to occurIlia Mirkin2015-02-201-0/+30
| | | | | | | | | | Because the TGSI interface creates merges for each instruction source and then splits them back out, there are a lot of unnecessary merge/split pairs which do essentially nothing. The various modifier/etc propagation doesn't know how to walk though those, so just remove them when they're unnecessary. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add support for new TGSI double opcodesIlia Mirkin2015-02-201-0/+236
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: handle zero and negative sqrt argumentsIlia Mirkin2015-02-201-2/+14
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: no instruction can load a double immediateIlia Mirkin2015-02-201-0/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix lowering of RSQ/RCP/SQRT/MOD to work with F64Ilia Mirkin2015-02-205-16/+40
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: fix F2F flipped stype/dtype flagsIlia Mirkin2015-02-201-2/+2
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: fix DSET boolean float flagIlia Mirkin2015-02-201-0/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gm107/ir: fix DMUL opcode encodingIlia Mirkin2015-02-201-3/+3
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gk110/ir: add emission of dadd/dmul/dmad opcodesIlia Mirkin2015-02-201-3/+77
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: add emission of dadd/dmul/dmad opcodes, fix minmaxIlia Mirkin2015-02-201-3/+63
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* mesa: don't enable NV_fragment_program_option with swrastRoland Scheidegger2015-02-211-1/+0
| | | | | | | | | | Since dropping some NV_fragment_program opcodes (commits 868f95f1da74cf6dd7468cba1b56664aad585ccb, a3688d686f147f4252d19b298ae26d4ac72c2e08) we can no longer parse all opcodes necessary for this extension, leading to bugs (https://bugs.freedesktop.org/show_bug.cgi?id=86980). Hence don't announce support for it in swrast (no other driver enabled it). (Note that remnants of some NV_fp/vp extensions remain, they could be dropped but are required as hacks for getting viewperf11 catia to run.)
* drivers/x11: add gallium include dirs to Makefile.amBrian Paul2015-02-201-0/+2
| | | | | | Fixes xlib driver build after e8c5cbfd921680c. Acked-by: Matt Turner <[email protected]>
* vbo: fix an unitialized-variable warningMarek Olšák2015-02-211-0/+1
| | | | | | | It looks like a bug to me. Cc: 10.5 10.4 10.3 <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/sw/kms: fix a type-mismatch warningMarek Olšák2015-02-211-1/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallium/sw/kms: don't redefine DEBUGMarek Olšák2015-02-211-7/+7
| | | | Reviewed-by: Brian Paul <[email protected]>
* targets/d3dadapter9: remove an unused variableMarek Olšák2015-02-211-1/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* tgsi: fix type-mismatch warningMarek Olšák2015-02-211-1/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* gallivm: fix uninitialized-variable warningsMarek Olšák2015-02-212-2/+2
| | | | Reviewed-by: Brian Paul <[email protected]>
* mesa: Have configure define NDEBUG, not mtypes.h.Matt Turner2015-02-202-3/+2
| | | | | | | | | | | | mtypes.h had been defining NDEBUG (used by assert) if DEBUG was not defined. Confusing and bizarre that you don't get NDEBUG if you don't include mtypes.h. ... which is just what happened in commit bef38f62e. Let's let configure define this for us if not using --enable-debug. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Fix the Mesa build without -DDEBUG.Kenneth Graunke2015-02-201-2/+2
| | | | | | | | | | | | | With -DDEBUG -UNDEBUG, this assert uses reg_state::stack_size, which doesn't exist, breaking the build: assert(state->states[index].index < state->states[index].stack_size); Switch it to ifndef NDEBUG, so the field will exist if the assertion actually generates code. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Drop dependency on mtypes.h for core NIR.Eric Anholt2015-02-203-1/+5
| | | | | | | | One less new directory necessary for gallium code that wants to interact with NIR. Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* glsl: Only include mtypes from glsl_types.h for the C++ code that needs it.Eric Anholt2015-02-201-1/+1
| | | | | | It's used in one of the methods, not in the structure definitions. Reviewed-by: Jose Fonseca <[email protected]>
* util: Move Mesa's bitset.h to util/.Eric Anholt2015-02-2012-10/+10
| | | | Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Make bitset.h not rely on Mesa-specific types and functions.Eric Anholt2015-02-201-4/+3
| | | | | | | | | | Note that we can't use u_math.h's align() because it's a function instead of a macro, while BITSET_DECLARE needs a constant expression for nouveau's usage in global declarations. v2: Stick some parens around the bits macro argument usage (review by Jose). Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Use u_math.h from macros.hEric Anholt2015-02-205-33/+1
| | | | | | | | | | This avoids duplication of some macros and other definitions across the tree. Note that COPY_4FV switches from a memcpy-based implementation to an assignment of 4 floats. Reviewed-by: Jose Fonseca <[email protected]>
* gallium/util: Don't include unused debug functions from u_math.hEric Anholt2015-02-201-1/+0
| | | | | | | It introduces references to gallium util/ symbols which means we don't get to include it from outside-of-gallium code. Reviewed-by: Jose Fonseca <[email protected]>
* mesa: Add gallium include dirs to more parts of the tree.Eric Anholt2015-02-2012-0/+24
| | | | | | v2: Try to patch up the scons bits. Reviewed-by: Jose Fonseca <[email protected]>
* gallium/radeon: fix an uninitialized-variable warningMarek Olšák2015-02-201-1/+1
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* gallium: add new double-related shader caps to all the gettersIlia Mirkin2015-02-205-0/+20
| | | | | | | | Missed a few drivers in the earlier changes, this should fix up all the ones that print unknown caps or don't have a default statement. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* svga: add missing _DROUND,DFRACEXP_DLDEXP_SUPPORTED switch casesBrian Paul2015-02-201-0/+2
| | | | To silence unhandled switch case warnings.
* radeonsi: don't use SQC_CACHES to flush ICACHE and KCACHE on SIMarek Olšák2015-02-201-18/+11
| | | | | | | | | | | | | | | This reverts 73c2b0d18c51459697d8ec194ecfc4438c98c139. It doesn't seem to be reliable. It's probably missing a wait packet or something, because it's just a register write and doesn't wait for anything. SURFACE_SYNC at least seems to wait until the flush is done. Just guessing. Let's not complicate things and revert this. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88561 Cc: 10.5 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* i965/gen6: Fix GL_GEOMETRY_SHADER_PRIMITIVES_EMITTED_ARBIago Toral Quiroga2015-02-201-0/+5
| | | | | | | | | | | | | | | | | | | In gen6 we need to compute the primitive count in the generated GS program. The current implementation only counts full primitives, that is, if the output primitive type is a triangle strip, it won't count individual triangles in the strip, only complete strips. If we want to count basic primitives instead we have two options: rework the assembly code we generate for strip primitives or simply use CL_INVOCATION_COUNT to resolve the query and let the hardware do that work for us. This patch implements the latter approach. Fixes the following piglit test: bin/arb_pipeline_statistics_query-geom -auto Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89210 Tested-by: Mark Janes <[email protected]> Reviewed-by: Ben Widawsky <[email protected]>
* mesa: Check that draw buffers are valid for glDrawBuffers on GLES3Eduardo Lima Mitev2015-02-201-0/+14
| | | | | | | | | | | | | Section 4.2 (Whole Framebuffer Operations) of the OpenGL 3.0 specification says: "Each buffer listed in bufs must be BACK, NONE, or one of the values from table 4.3 (NONE, COLOR_ATTACHMENTi)". Fixes 1 dEQP test: * dEQP-GLES3.functional.negative_api.buffer.draw_buffers Reviewed-by: Matt Turner <[email protected]>
* glsl: don't allow invariant qualifiers for interface blocksSamuel Iglesias Gonsalvez2015-02-201-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GLSL 1.50 and GLSL 4.40 specs, they both say the same in "Interface Blocks" section: "If optional qualifiers are used, they can include interpolation qualifiers, auxiliary storage qualifiers, and storage qualifiers and they must declare an input, output, or uniform member consistent with the interface qualifier of the block" From GLSL ES 3.0, chapter 4.3.7 "Interface Blocks", page 38: "GLSL ES 3.0 does not support interface blocks for shader inputs or outputs." and from GLSL ES 3.0, chapter 4.6.1 "The invariant qualifier", page 52. "Only variables output from a shader can be candidates for invariance." This patch fixes the following dEQP tests: dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_uniform_block_2_vertex dEQP-GLES3.functional.shaders.declarations.invalid_declarations.invariant_uniform_block_2_fragment No piglit regressions. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> v2: - Enable this check for GLSL. Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* vc4: Keep an array of pointers to instructions defining the temps around.Eric Anholt2015-02-198-68/+67
| | | | | The optimization passes are always regenerating it and throwing it away, but it's not hard to keep track of.
* vc4: Move qir_uniform() and the constant-value versions to vc4_qir.c/h.Eric Anholt2015-02-193-45/+49
| | | | | I may want them in optimization passes, and they're not really particular to the program translation stage.
* vc4: Enforce one-uniform-per-instruction after optimization.Eric Anholt2015-02-196-50/+209
| | | | | | | | | | | | | | | This lets us more intelligently decide which uniform values should be put into temporaries, by choosing the most reused values to push to temps first. total uniforms in shared programs: 13457 -> 13433 (-0.18%) uniforms in affected programs: 1524 -> 1500 (-1.57%) total instructions in shared programs: 40198 -> 40019 (-0.45%) instructions in affected programs: 6027 -> 5848 (-2.97%) I noticed this opportunity because with the NIR work, some programs were happening to make different uniform copy propagation choices that significantly increased instruction counts.
* vc4: Rename add_uniform() to qir_uniform().Eric Anholt2015-02-191-15/+15
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* vc4: Shut up runtime warnings about new pipe caps.Eric Anholt2015-02-191-0/+2
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* i965/vec4: Add and use byte-MOV instruction for unpack 4x8.Matt Turner2015-02-194-2/+21
| | | | | | | | | Previously we were using a B/UB source in an Align16 instruction, which is illegal. It for some reason works on all platforms, except Broadwell. Cc: "10.5" <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86811 Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Emit MADs.Matt Turner2015-02-192-4/+11
| | | | | | Low hanging fruit: cuts a couple of instructions. Reviewed-by: Ian Romanick <[email protected]>
* i965/blorp: Optimize clamping tex coords.Matt Turner2015-02-192-4/+22
| | | | | | | | | | | Each emit_cond_mov() emits a CMP of its first to arguments using the specified conditional mod, followed by a predicated MOV of the fifth argument into the fourth. In all four cases here, it was just implementing MIN/MAX which we can do in a single SEL instruction. Also reorder the instructions for a slightly better schedule. Reviewed-by: Ian Romanick <[email protected]>
* i965: Use greater-equal cmod to implement maximum.Matt Turner2015-02-194-7/+10
| | | | | | | | The docs specifically call out SEL with .l and .ge as the implementations of MIN and MAX respectively. Among other things, SEL with these conditional mods are commutative. Reviewed-by: Ian Romanick <[email protected]>
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