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* xvmc: fix string comparisonEric Engestrom2019-02-071-3/+3
| | | | | | | Fixes: 6fca18696d0e6a243f6f "g3dvl: Update XvMC unit tests." Cc: Younes Manton <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> (cherry picked from commit 40b53a72033a601ab474c5f8e27eb5ca2c8bad6c)
* xvmc: fix string comparisonEric Engestrom2019-02-071-10/+10
| | | | | | | | Fixes: c7b65dcaffeb9d0760c8 "xvmc: Define some Xv attribs to allow users to specify color standard and procamp" Cc: Christian König <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> (cherry picked from commit 110a6e1839bcf31e3592389ad55a7ba07b551965)
* freedreno: a2xx: fix fast clearJonathan Marek2019-02-061-1/+0
| | | | | | | | Fixes: 912a9c8d Signed-off-by: Jonathan Marek <[email protected]> Cc: 19.0 <[email protected]> (cherry picked from commit 3361305f570505e0131c570041779496d0b9c663)
* Version: Bump for rc2mesa-19.0.0-rc2Dylan Baker2019-02-051-1/+1
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* anv: wire up the state_pool_padding testEmil Velikov2019-02-051-0/+5
| | | | | | | | | | Cc: Jason Ekstrand <[email protected]> Fixes: 927ba12b53c ("anv/tests: Adding test for the state_pool padding.") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Rafael Antognolli <[email protected]><Paste> Reviewed-by: Dylan Baker <[email protected]> (cherry picked from commit 8943eb8f03fe67710ce65fc0a54024751ff2b5bd)
* loader/dri3: Use strlen instead of sizeof for creating VRR property atomMichel Dänzer2019-02-051-1/+1
| | | | | | | | | | | | sizeof counts the terminating null character as well, so that also contributed to the ID computed for the X11 atom. But the convention is for only the non-null characters to contribute to the atom ID. Fixes: 2e12fe425fe3 "loader/dri3: Enable adaptive_sync via _VARIABLE_REFRESH property" Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Eric Anholt <[email protected]> (cherry picked from commit c0a540f32067cc8cb126d9aa1eb12a11cf15373a)
* radeonsi: fix crashing performance counters (division by zero)Marek Olšák2019-02-051-1/+1
| | | | | Fixes: e2b9329f17 "radeonsi: move remaining perfcounter code into si_perfcounter.c" (cherry picked from commit 742d6cdb42e5570a3a74005f18bb89208069d01f)
* anv: Fix VK_EXT_transform_feedback working with varyings packed in PSIZDanylo Piliaiev2019-02-041-3/+20
| | | | | | | | | | | | | | Transform feedback did not set correct SO_DECL.ComponentMask for varyings packed in VARYING_SLOT_PSIZ: gl_Layer - VARYING_SLOT_LAYER in VARYING_SLOT_PSIZ.y gl_ViewportIndex - VARYING_SLOT_VIEWPORT in VARYING_SLOT_PSIZ.z gl_PointSize - VARYING_SLOT_PSIZ in VARYING_SLOT_PSIZ.w Fixes: 36ee2fd61c8f94 "anv: Implement the basic form of VK_EXT_transform_feedback" Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> (cherry picked from commit 64d3b148fe71453c296ba9525f49ffe728171582)
* intel/fs: Do the grf127 hack on SIMD8 instructions in SIMD16 modeJason Ekstrand2019-02-041-7/+6
| | | | | | | | | | | | Previously, we only applied the fix to shaders with a dispatch mode of SIMD8 but the code it relies on for SIMD16 mode only applies to SIMD16 instructions. If you have a SIMD8 instruction in a SIMD16 shader, neither would trigger and the restriction could still be hit. Fixes: 232ed8980217dd "i965/fs: Register allocator shoudn't use grf127..." Reviewed-by: Jose Maria Casanova Crespo <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> (cherry picked from commit b4f0d062cd12b4f675bac900ac41d1085a79239a)
* st/mesa: Fix topogun-1.06-orc-84k-resize.trace crashNeha Bhende2019-02-011-0/+4
| | | | | | | | | | | | | | We need to initialize all fields in rs->prim explicitly while creating new rastpos stage. Fixes: bac8534267 ("st/mesa: allow glDrawElements to work with GL_SELECT feedback") v2: Initializing all fields in rs->prim as per Ilia. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> (cherry picked from commit 69d736b17a96a4d7a21c3c88fd787091acc1def0)
* v3d: Fix leak in resource setup error pathErnestas Kulik2019-01-311-1/+1
| | | | | | | | | | Reported by Coverity: in the case of unsupported modifier request, the code does not jump to the “fail” label to destroy the acquired resource. CID: 1435704 Signed-off-by: Ernestas Kulik <[email protected]> Fixes: 45bb8f295710 ("broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.") (cherry picked from commit 90458bef544ac46a912f06e73f71c3cb20fdaaf6)
* v3d: Fix image_load_store clamping of signed integer stores.Eric Anholt2019-01-311-1/+1
| | | | | | | | | This was copy-and-paste fail, that oddly showed up in the CTS's reinterprets of r32f, rgba8, and srgba8 to rgba8i, but not r32ui and r32i to rgba8i or reinterprets to other signed int formats. Fixes: 6281f26f064a ("v3d: Add support for shader_image_load_store.") (cherry picked from commit ab4d5775b0decad7df56245cecad63912ed62b4c)
* mesa: Skip partial InvalidateFramebuffer of packed depth/stencil.Eric Anholt2019-01-311-0/+23
| | | | | | | | | | | One of the CTS cases tries to invalidate just stencil of packed depth/stencil, and we incorrectly lost the depth contents. Fixes dEQP-GLES3.functional.fbo.invalidate.whole.unbind_read_stencil Fixes: 0c42b5f3cb90 ("mesa: wire up InvalidateFramebuffer") Reviewed-by: Marek Olšák <[email protected]> (cherry picked from commit db2ae51121067b66d4ee8313ba7f74cecb201a03)
* freedreno: more fixing release tarballRob Clark2019-01-311-1/+3
| | | | | | Fixes: aa0fed10d35 freedreno: move ir3 to common location Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit 39cfdf9930659b01cd89f0fbc29c43c623e17d2d)
* freedreno: fix release tarballRob Clark2019-01-311-0/+1
| | | | | | | Fixes: b4476138d5a freedreno: move drm to common location Reviewed-by: Eric Engestrom <[email protected]> Signed-off-by: Rob Clark <[email protected]> (cherry picked from commit e252656d1481e5bbc6bf34beb01076b329073ac7)
* radv/winsys: fix hash when adding internal buffersSamuel Pitoiset2019-01-311-1/+1
| | | | | | | | | This fixes serious stuttering in Shadow Of The Tomb Raider. Fixes: 50fd253bd6e ("radv/winsys: Add priority handling during submit.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> (cherry picked from commit 9c762c01c8f69e8209935d902648cb174de8c8bf)
* vc4: Fix leak in HW queries error pathErnestas Kulik2019-01-311-1/+1
| | | | | | | | | | | Reported by Coverity: in the case where there exist hardware and non-hardware queries, the code does not jump to err_free_query and leaks the query. CID: 1430194 Signed-off-by: Ernestas Kulik <[email protected]> Fixes: 9ea90ffb98fb ("broadcom/vc4: Add support for HW perfmon") (cherry picked from commit f6e49d5ad0fde19a074644491475470d684dd721)
* vc4: Declare the last cpu pointer as being modified in NEON asm.Emil Velikov2019-01-311-2/+1
| | | | | | | | | | | | Earlier commit addressed 7 of the 8 instances available. v2: Rebase patch back to master (by anholt) Cc: Carsten Haitzler (Rasterman) <[email protected]> Cc: Eric Anholt <[email protected]> Fixes: 300d3ae8b14 ("vc4: Declare the cpu pointers as being modified in NEON asm.") Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit 385843ac3ce1b868d9e24fcb2dbc0c8d5f5a7c99)
* VERSION: bump to 19.0.0-rc1mesa-19.0.0-rc1mesa-19.0-rc1Dylan Baker2019-01-301-1/+1
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* android,autotools,i965: Fix location of float64_glsl.hDylan Baker2019-01-303-2/+4
| | | | | | | | | | | Android.mk and autotools disagree about where generated files should go, which wasn't a problem until we wanted to build a dist tarball. This corrects the problme by changing the output and include paths to be the same on android and autotools (meson already has the correct include path). Fixes: 7d7b30835cfb9eb89beca9fb8593d0954f79b84d ("automake: Fix path to generated source")
* automake: Add --enable-autotools to distcheck flagsDylan Baker2019-01-301-0/+1
| | | | | Fixes: e68777c87ceed02ab199b32f941778c3cf97c794 ("autotools: Deprecate the use of autotools")
* configure: Bump SWR LLVM requirement to 7Dylan Baker2019-01-301-3/+3
| | | | | | | | | | | | | | | | | It is currently impossible to build a dist tarball that works when SWR requires LLVM 6. To generate the tarball we'd need to configure with LLVM 6, which is fine. But to build the dist check we need LLVM 7, as RadeonSI and RadV require that version. Unfortunately the headers genererated with LLVM 6 don't compile with LLVM 7, the API has changed between the two versions. I weighed a couple of options here. One would be to ship an unbootstrapped tarball generated with meson. This would fix the issue by not bootstrapping, so whatever version of LLVM used would work because the SWR headers would be generated at compile time. Unfortunately this would involve some heavy modifications to the infastructure used to upload the tarballs, and I've decided not to persue this.
* automake: Add include dir for nir src directory19.0-branchpointDylan Baker2019-01-291-0/+1
| | | | | | Fixes: 6281f26f064ada36b57d45feb68d8e7d783198c9 ("v3d: Add support for shader_image_load_store.") Reviewed-by: Jordan Justen <[email protected]>
* automake: Add float64.glsl to dist tarballDylan Baker2019-01-291-0/+1
| | | | | | Fixes: b63a1f8e40b6705d6a1d806fbd38dcd197d4229b ("glsl: Create file to contain software fp64 functions") Reviewed-by: Jordan Justen <[email protected]>
* automake: Fix path to generated sourceDylan Baker2019-01-291-1/+1
| | | | | | Fixes: b63a1f8e40b6705d6a1d806fbd38dcd197d4229b ("glsl: Create file to contain software fp64 functions") Reviewed-by: Jordan Justen <[email protected]>
* nir: Optimize double-precision lower_round_even()Matt Turner2019-01-291-44/+12
| | | | | | | | | | | Use the trick of adding and then subtracting 2**52 (52 is the number of explicit mantissa bits a double-precision floating-point value has) to implement round-to-even. Cuts the number of instructions on SKL of the piglit test fs-roundEven-double.shader_test from 109 to 21. Reviewed-by: Roland Scheidegger <[email protected]>
* ac: use the correct LLVM processor name on Raven2Marek Olšák2019-01-291-1/+1
| | | | Reviewed-by: Alex Deucher <[email protected]>
* v3d: Fix the autotools build.Eric Anholt2019-01-291-1/+1
| | | | Noticed while looking at the gitlab-CI MR.
* freedreno: fix sysmem rendering being used when clear is usedJonathan Marek2019-01-291-1/+1
| | | | | | | | | | This batch->cleared value is only used to decide to use sysmem rendering or not, so it should include any buffers that are affected by a clear. This is required because the a2xx fast clear doesn't work with sysmem rendering. The a22x "normal" clear path doesn't work with sysmem either. Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: fix depth usage logicJonathan Marek2019-01-291-2/+6
| | | | | | | | Depth can be used even when there is no restore/resolve of depth. This happens when the depth buffer is invalidated after rendering to avoid the resolve operation. Signed-off-by: Jonathan Marek <[email protected]>
* freedreno: fix invalidate logicJonathan Marek2019-01-292-10/+10
| | | | | | | | Set dirty bits on invalidate to trigger invalidate logic in fd_draw_vbo. Also, resource_written for color needs to be after the invalidate logic. Signed-off-by: Jonathan Marek <[email protected]>
* mesa/st: wire up DiscardFramebufferJonathan Marek2019-01-291-0/+25
| | | | | Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: wire up InvalidateFramebufferRob Clark2019-01-292-7/+66
| | | | | | | | | | And before someone actually starts implementing DiscardFramebuffer() lets rework the interface to something that is actually usable. Signed-off-by: Rob Clark <[email protected]> Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* st/dri: invalidate_resource depth/stencil before flush_resourceJonathan Marek2019-01-291-7/+7
| | | | | | | | | | | | This allows freedreno to be aware of the depth invalidate when flushing batches on flush_resource. AFAIK, the only other driver which might care about this change is vc4, where I think it should help by allowing the depth invalidate to work with GALLIUM_HUD. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* egl/wayland-drm: Only announce formats via wl_drm which the driver supports.Mario Kleiner2019-01-295-5/+51
| | | | | | | | | | | | | | | | | | | | | Check if a pixel format is supported by the Wayland servers gpu driver before exposing it to the client via wl_drm, so we avoid reporting formats to the client which the server gpu can't handle. Restrict this reporting to the new color depth 30 formats for now, as the ARGB/XRGB8888 and RGB565 formats are probably supported by every gpu under the sun. Atm. this is mostly useful to allow proper PRIME renderoffload for depth 30 formats on the typical Intel iGPU + NVidia dGPU "NVidia Optimus" laptop combo. Tested on Intel, AMD, NVidia with single-gpu setup and on a Intel + NVidia Optimus setup. Signed-off-by: Mario Kleiner <[email protected]> Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* egl/wayland: Allow client->server format conversion for PRIME offload. (v2)Mario Kleiner2019-01-291-9/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support PRIME render offload between a Wayland server gpu and a Wayland client gpu with different channel ordering for their color formats, e.g., between Intel drivers which currently only support ARGB2101010 and XRGB2101010 import/display and nouveau which only supports ABGR2101010 rendering and display on nv-50 and later. In the wl_visuals table, we also store for each format an alternate sibling format which stores colors at the same precision, but with different channel ordering, e.g., ARGB2101010 <-> ABGR2101010. If a given client-gpu renderable format is not supported by the server for import, but the alternate format is supported by the server, expose the client-gpu renderable format as a valid EGLConfig to the client. At eglSwapBuffers time, during the blitImage() detiling blit from the client backbuffer to the linear buffer, the client format is converted to the server supported format. As we have to do a copy for PRIME anyway, this channel swizzling conversion comes essentially for free. Note that even if a server gpu in principle does support sampling from the clients native format, this conversion will be a performance advantage if it allows to convert to the servers preferred format for direct scanout, as the Wayland compositor may then be able to directly page-flip a fullscreen client wl_buffer onto the primary plane, or onto a hardware overlay plane, avoiding an extra data copy for desktop composition. Tested so far under Weston with: nouveau single-gpu, Intel single-gpu, AMD single-gpu, "Optimus" Intel server iGPU for display + NVidia client dGPU for rendering. v2: Implement minor review comments by Eric Engestrom: Add some comment and assert, and some style fixes for clarity. No functional change. Signed-off-by: Mario Kleiner <[email protected]> Reviewed-by: Adam Jackson <[email protected]> Reviewed-by: Daniel Stone <[email protected]>
* intel/fs: Use split sends for surface writes on gen9+Jason Ekstrand2019-01-292-18/+47
| | | | | | | | | | | | | Surface reads don't need them because they just have the one address payload. With surface writes, on the other hand, we can put the address and the data in the different halves and avoid building the payload all together. The decrease in register pressure and added freedom in register allocation resulting from this change reduces spilling enough to improve the performance of one customer benchmark by about 2x. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Add interference between SENDS sourcesJason Ekstrand2019-01-291-0/+27
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Support SENDS in SHADER_OPCODE_SENDJason Ekstrand2019-01-293-8/+66
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/disasm: Properly disassemble split sendsJason Ekstrand2019-01-291-19/+142
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/eu: Add support for the SENDS[C] messagesJason Ekstrand2019-01-294-19/+255
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/inst: Indent some codeJason Ekstrand2019-01-291-177/+183
| | | | | | | We're about to add some more if cases so let's have the giant re-indent in it's own patch to make review easier. Acked-by: Iago Toral Quiroga <[email protected]>
* intel/inst: Fix the ia16_addr_imm helpersJason Ekstrand2019-01-291-4/+5
| | | | | | | | These have clearly never seen any use.... On gen8, the bottom 4 bits are missing so we need to shift them off before we call set_bits and shift again when we get the bits. Found by inspection. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/disasm: Rework SEND decoding to use descriptorsJason Ekstrand2019-01-291-36/+50
| | | | | | | | | | | | Instead of fetching the information out of the instruction directly, fetch the descriptor and then pluck the information out of the descriptor. The current scheme works ok for SEND but with SENDS, it all falls to pieces because the descriptor is completely shuffled around. This commit doesn't actually convert everything. One notable exception is URB messages which don't even use descriptors in emit_urb_WRITE yet. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/eu: Add more message descriptor helpersJason Ekstrand2019-01-291-27/+216
| | | | | | | | | | | | | | | | We want to be able to extract data from descriptors as well as unify a bit of the descriptor construction. One of the unifications we do is to unify the read/write and dataport descriptors. On gen4-5, read/write are substantially different and the read descriptors change between gen4 and gen4.x. On gen6, they unified layouts between read, write, and dataport. Then, on gen8, they added one bit to the message type field but left it reserved MBZ for read/write messages. This commit chooses to treat that as if they expanded the field everywhere and just didn't have enough enum values for read/write to bother with the extra bit. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/eu/validate: SEND restrictions also apply to SENDCJason Ekstrand2019-01-291-1/+2
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/eu: Use GET_BITS in brw_inst_set_send_ex_descJason Ekstrand2019-01-291-5/+5
| | | | | | It's a bit more readable Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+Jason Ekstrand2019-01-297-88/+25
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Use SHADER_OPCODE_SEND for texturing on gen7+Jason Ekstrand2019-01-294-142/+177
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Use a logical opcode for IMAGE_SIZEJason Ekstrand2019-01-294-6/+21
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
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