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* i965: Combine assembly annotations if possible.Matt Turner2015-11-121-5/+18
* i965: Set annotation_info's mem_ctx.Matt Turner2015-11-123-2/+5
* i965: Don't consider control flow instructions to have sources.Matt Turner2015-11-121-8/+8
* i965: Fill out instruction list.Matt Turner2015-11-123-14/+42
* ralloc: Set *start in ralloc_vasprintf_rewrite_tail() if str is NULL.Matt Turner2015-11-121-0/+1
* i965: Consolidate is_3src() functions.Matt Turner2015-11-123-8/+7
* st/wgl: add a comment about recursive locking in stw_make_current()Brian Paul2015-11-121-0/+4
* st/wgl: add a lock assertion in stw_framebuffer_from_hwnd_locked()Brian Paul2015-11-121-0/+1
* st/wgl: add some mutex checking codeJosé Fonseca2015-11-121-0/+26
* st/wgl: rename stw_framebuffer_release() to stw_framebuffer_unlock()Brian Paul2015-11-125-19/+19
* st/wgl: reimplement stw_framebuffer::mutex with CRITICAL_SECTIONBrian Paul2015-11-124-29/+32
* st/wgl: include u_debug.hBrian Paul2015-11-123-0/+6
* st/wgl: reimplement stw_device::fb_mutex with CRITICAL_SECTIONBrian Paul2015-11-123-15/+29
* st/wgl: re-implement stw_device::ctx_mutex with CRITICAL_SECTIONBrian Paul2015-11-123-19/+34
* gallium/hud: add cpu graph support for WindowsBrian Paul2015-11-121-0/+54
* glsl: set matrix_stride for non matrices with atomic counter buffersTapani Pälli2015-11-121-0/+2
* mesa: validate precision of varyings during ValidateProgramPipelineTapani Pälli2015-11-123-0/+80
* glsl: do not lose precision information when packing varyingsTapani Pälli2015-11-121-0/+1
* glsl: Add precision information to ir_variableIago Toral Quiroga2015-11-124-24/+303
* glsl: Move the definition of precision_qualifier_allowedIago Toral Quiroga2015-11-121-36/+35
* glsl: Add user-defined default precision qualifiers to the symbol tableIago Toral Quiroga2015-11-121-19/+10
* glsl: Add default precision qualifiers to the symbol tableIago Toral Quiroga2015-11-121-0/+12
* glsl: Add API to put default precision qualifiers in the symbol tableIago Toral Quiroga2015-11-122-0/+26
* i965/fs/nir: fix the number of register written by FS_OPCODE_GET_BUFFER_SIZESamuel Iglesias Gonsálvez2015-11-121-2/+14
* i965/skl/gt4: Fix URB programming restriction.Ben Widawsky2015-11-111-0/+9
* nv50,nvc0: add ARB_clear_texture supportIlia Mirkin2015-11-117-8/+103
* st/mesa: implement ARB_clear_textureIlia Mirkin2015-11-112-0/+30
* gallium: add PIPE_CAP_CLEAR_TEXTURE and clear_texture prototypeIlia Mirkin2015-11-1118-0/+31
* glsl: add helper to check for enhanced layouts supportTimothy Arceri2015-11-121-0/+5
* mesa: add ARB_enhanced_layoutsTimothy Arceri2015-11-125-0/+6
* r600: initialised PGM_RESOURCES_2 for ES/GSDave Airlie2015-11-122-0/+6
* i965: Split nir_emit_intrinsic by stage with a general fallback.Kenneth Graunke2015-11-112-277/+381
* mesa/copyimage: allow width/height to not be multiples of blockIlia Mirkin2015-11-111-3/+34
* i965/brw_reg: Add a brw_VxH_indirect helperJason Ekstrand2015-11-111-0/+11
* mesa: remove old comments in arrayobj.cBrian Paul2015-11-111-5/+0
* st/wgl: clarify code in stw_framebuffer_from_hwnd_locked()Brian Paul2015-11-111-2/+2
* st/wgl: improve some function commentsBrian Paul2015-11-111-6/+30
* st/wgl: whitespace/formatting fixesBrian Paul2015-11-113-63/+48
* st/wgl: fix locking issue in stw_st_framebuffer_present_locked()Brian Paul2015-11-111-0/+3
* i965: Print force_writemask_all in dump_instructions().Kenneth Graunke2015-11-112-0/+6
* i965: Combine BRW_NEW_*_BINDING_TABLE dirty bits.Kenneth Graunke2015-11-115-26/+14
* i965: Map GL_PATCHES to 3DPRIM_PATCHLIST_n.Kenneth Graunke2015-11-112-1/+10
* docs: add news item and link release notes for 11.0.5Emil Velikov2015-11-112-0/+7
* docs: add sha256 checksums for 11.0.5Emil Velikov2015-11-111-1/+2
* docs: add release notes for 11.0.5Emil Velikov2015-11-111-0/+173
* r600g: Pass conservative depth parameters to hwGlenn Kennard2015-11-117-1/+53
* Revert "r600g: Pass conservative depth parameters to hw"Dave Airlie2015-11-116-46/+0
* r600g: Implement ARB_texture_viewGlenn Kennard2015-11-114-9/+20
* r600g: Pass conservative depth parameters to hwGlenn Kennard2015-11-116-0/+46
* i965/nir/opt_peephole_ffma: Bypass fusion if any operand of fadd and fmul is ...Eduardo Lima Mitev2015-11-101-0/+31
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