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* glsl: assign hidden uniforms their slot id earlierTimothy Arceri2015-09-171-49/+41
| | | | | | | | | | | | This is required so that the next patch can safely assign the slot id to the var. The ids are now assigned in the order we want before allocating storage so there is no need to sort the storage array and move things around. V2: rename variable to make code easier to follow as suggested by Jason Reviewed-by: Jason Ekstrand <[email protected]>
* glsl: order indices for samplers inside a struct arrayTimothy Arceri2015-09-172-18/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This allows the correct offset to be easily calculated for indirect indexing when a struct array contains multiple samplers, or any crazy nesting. The indices for the folling struct will now look like this: Sampler index: 0 Name: s[0].tex Sampler index: 1 Name: s[1].tex Sampler index: 2 Name: s[0].si.tex Sampler index: 3 Name: s[1].si.tex Sampler index: 4 Name: s[0].si.tex2 Sampler index: 5 Name: s[1].si.tex2 Before this change it looked like this: Sampler index: 0 Name: s[0].tex Sampler index: 3 Name: s[1].tex Sampler index: 1 Name: s[0].si.tex Sampler index: 4 Name: s[1].si.tex Sampler index: 2 Name: s[0].si.tex2 Sampler index: 5 Name: s[1].si.tex2 struct S_inner { sampler2D tex; sampler2D tex2; }; struct S { sampler2D tex; S_inner si; }; uniform S s[2]; V3: Update comments with suggestions from Jason V2: rename struct array counter to have better name Reviewed-by: Jason Ekstrand <[email protected]>
* Revert "mesa/extensions: restrict GL_OES_EGL_image to GLES"Dave Airlie2015-09-171-1/+2
| | | | | | | | | | | | | This reverts commit 48961fa3ba37999a6f8fd812458b735e39604a95. glamor/Xwayland use this, the spec saying something when it was written, and the fact that the comment says Mesa relies on it hasn't changed. I also don't have a copy of this patch in my mail archive, which seems wierd, did it get posted to mesa-dev? Signed-off-by: Dave Airlie <[email protected]>
* vc4: Only build in simulator mode if we find pkg-config for it.Eric Anholt2015-09-161-5/+2
| | | | This will let other developers build it x86 for build-testing purposes.
* freedreno/a3xx: use NUM_USER_CLIP_PLANES helper instead of magic numberIlia Mirkin2015-09-161-1/+2
| | | | | | Use the helper from the newly-updated generated header file. Signed-off-by: Ilia Mirkin <[email protected]>
* freedreno/a3xx: fix blending of L8 formatIlia Mirkin2015-09-161-0/+2
| | | | | | | | Even though luminance formats don't have alpha, we still want the alpha output to go to the blender. This fixes the luminance blending tests. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0" <[email protected]>
* freedreno/a3xx: add support for dual-source blendingIlia Mirkin2015-09-168-6/+33
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* vc4: convert from tgsi semantic/index to varying-slotEric Anholt2015-09-167-147/+106
| | | | | | | | | (originally part of previous patch, split out to separate patch by Rob) v2: squash in some fixes from Eric v3: Another fix from Eric for point coords. Signed-off-by: Rob Clark <[email protected]>
* gallium/ttn: Convert to using VARYING_SLOT_* / FRAG_RESULT_*.Eric Anholt2015-09-166-47/+239
| | | | | | | | | | | | | | | This avoids exceeding the size of the .index bitfield since it got truncated, and should make our NIR look more like the NIR that the rest of the NIR developers are working on. v2: split out vc4 updates, first patch uses varying_slot_to_tgsi_semantic() helper, and second patch does the actual conversion. v3: add frag_result_to_tgsi_semantic() helper and don't try to map frag_results to semantic name/index as if they were varying_slot's v4: use VERT_ATTRIB_ for VS inputs v5: Fix vc4 build. Signed-off-by: Rob Clark <[email protected]>
* nv50, nvc0: fix max texture buffer size to 128M elementsIlia Mirkin2015-09-162-2/+2
| | | | | | | | This is what the hardware supports, there never was any sort of 64K limit. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]>
* st/mesa: avoid integer overflows with buffers >= 512MBIlia Mirkin2015-09-161-2/+2
| | | | | | | | | This fixes failures with the newly-submitted max-size texture buffer piglit test for GPUs exposing >= 128M max texels. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "10.6 11.0" <[email protected]> Reviewed-by: Glenn Kennard <[email protected]>
* mesa: move GL_APPLE_object_purgeable functions to new fileBrian Paul2015-09-166-388/+461
| | | | | | | Move this code out of bufferobj.c since it's not strongly connected to buffer objects. Acked-by: Matt Turner <[email protected]>
* mesa: remove trailing whitespace in bufferobj.cBrian Paul2015-09-161-7/+7
| | | | Trivial.
* mesa: whitespace, line wrap fixes in varray.cBrian Paul2015-09-161-12/+20
| | | | Trivial.
* nir/print: print symbolic names from shader-enumRob Clark2015-09-161-3/+42
| | | | | | | | | v2: split out moving of FILE *fp into state structure into it's own (more complete patch) to reduce the noise in this one Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir/print: bit of state refactoringRob Clark2015-09-161-109/+152
| | | | | | | | | | | | Rename print_var_state to print_state, and stuff FILE ptr into the state object. This avoids passing around an extra parameter everywhere. v2: even more extensive conversion.. use state *everywhere* instead of FILE ptr, and convert nir_print_instr() to use state as well Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Connor Abbott <[email protected]>
* glsl: shader-enum to name debug fxnsRob Clark2015-09-164-1/+261
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* freedreno: one screen to rule them allRob Clark2015-09-165-5/+126
| | | | | | | | | | Similar to fee0686c21c631d96d6042741267a3c218c23ffc, but in this case to ensure that drm_gralloc and libGLES_mesa are sharing a single screen. Bumps libdrm_freedreno version dependency, as it requires the new fd_device_fd() API. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: use NIR to lower ffract instead of tgsi_loweringRob Clark2015-09-161-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* nir: add lowering for ffractRob Clark2015-09-162-0/+4
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965/fs: The barrier send uses only 1 payload registerJordan Justen2015-09-152-2/+5
| | | | | | | | | | | | | | | | | | | When preparing the barrier payload, the instructions should operate in simd8 mode since we only use 1 payload register. fs_inst::regs_read is also updated to indicate that it only reads one register for SHADER_OPCODE_BARRIER. These issues were flagged by: commit cadd7dd384b33a779d46bd664f456bed4a21a5b7 Author: Jason Ekstrand <[email protected]> Date: Thu Jul 2 15:41:02 2015 -0700 i965/fs: Add a very basic validation pass Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir/builder: Use a normal temporary array in nir_channelJason Ekstrand2015-09-151-1/+2
| | | | | | | | C++ gets cranky if we take references of temporaries. This isn't a problem yet in master because nir_builder is never used from C++. However, it will be in the future so we should fix it now. Reviewed-by: Rob Clark <[email protected]>
* freedreno/a4xx: more texture formatsRob Clark2015-09-151-7/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: border-color supportRob Clark2015-09-154-2/+31
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: wire up texture clamp loweringRob Clark2015-09-152-20/+80
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: helper for a3xx/a4xx border-colorsRob Clark2015-09-154-67/+99
| | | | | | | | Both use the same layout for the buffer containing border-color values, so rather than duplicating the logic in a4xx, split it out into a helper. Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2015-09-155-17/+37
| | | | Signed-off-by: Rob Clark <[email protected]>
* nir/lower_vec_to_movs: Coalesce into destinations of fdot instructionsJason Ekstrand2015-09-151-13/+36
| | | | | | | | | | | | | | | | | | | Now that we have a replicating fdot instruction, we can actually coalesce into the destinations of vec4 instructions. We couldn't really do this before because, if the destination had to end up in .z, we couldn't reswizzle the instruction. With a replicated destination, the result ends up in all channels so we can just set the writemask and we're done. Shader-db results for vec4 programs on Haswell: total instructions in shared programs: 1747753 -> 1746280 (-0.08%) instructions in affected programs: 143274 -> 141801 (-1.03%) helped: 667 HURT: 0 It turns out that dot-products matter... Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965/vec4: Use the replicated fdot instruction in NIRJason Ekstrand2015-09-152-3/+11
| | | | | Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir: Add a fdot instruction that replicates the result to a vec4Jason Ekstrand2015-09-153-0/+12
| | | | | | | | Fortunately, nir_constant_expr already auto-splats if "dst" never shows up in the constant expression field so we don't need to do anything there. Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir/lower_vec_to_movs: Coalesce movs on-the-fly when possibleJason Ekstrand2015-09-151-0/+85
| | | | | | | | | | | | | | | | | | | The old pass blindly inserted a bunch of moves into the shader with no concern for whether or not it was really needed. This adds code to try and coalesce into the destination of the instruction providing the value. Shader-db results for vec4 shaders on Haswell: total instructions in shared programs: 1754420 -> 1747753 (-0.38%) instructions in affected programs: 231230 -> 224563 (-2.88%) helped: 1017 HURT: 2 This approach is heavily based on a different patch by Eduardo Lima Mitev <[email protected]>. Eduardo's patch did this in a separate pass as opposed to integrating it into nir_lower_vec_to_movs. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir/lower_vec_to_movs: Get rid of start_idx and swizzle compactingJason Ekstrand2015-09-151-20/+13
| | | | | | | | | | | | | Previously, we did this thing with keeping track of a separate start_idx which was different from the iteration variable. I think this was a relic of the way that GLSL IR implements writemasks. In NIR, if a given bit in the writemask is unset then that channel is just "unused", not missing. In particular, a vec4 operation with a writemask of 0xd will use sources 0, 2, and 3 and leave source 1 alone. We can simplify things a good deal (and make them correct) by removing this "compacting" step. Reviewed-by: Eduardo Lima Mitev <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965/vec4_nir: Use partial SSA form rather than full non-SSAJason Ekstrand2015-09-153-4/+20
| | | | | | | | | We made this switch in the FS backend some time ago and it seems to make a number of things a bit easier. In particular, supporting SSA values takes very little work in the backend and allows us to take advantage of the majority of the SSA information even after we've gotten rid of Phi nodes. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir/lower_vec_to_movs: Handle partially SSA shadersJason Ekstrand2015-09-151-6/+15
| | | | | | | | v2 (Jason Ekstrand): - Use nir_instr_rewrite_dest - Pass the impl directly into lower_vec_to_movs_block Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir/lower_vec_to_movs: Pass the shader around directlyJason Ekstrand2015-09-151-6/+8
| | | | | | | | Previously, we were passing the shader around, we were just calling it "mem_ctx". However, the nir_shader is (and must be for the purposes of mark-and-sweep) the mem_ctx so we might as well pass it around explicitly. Reviewed-by: Eduardo Lima Mitev <[email protected]>
* i965/fs: Add a very basic validation passJason Ekstrand2015-09-154-0/+69
| | | | | | | | Currently the validation pass only validates that regs_read and regs_written are consistent with the sizes of VGRF's. We can add more as we find it to be useful. Reviewed-by: Matt Turner <[email protected]>
* i965/fs_surface_builder: Only apply predicate to components that existJason Ekstrand2015-09-151-1/+1
| | | | | | | | | | | | In certain conditions, we have to do bounds-checking in the shader for image_load_store. The way this works for image loads is that we do a predicated load and then emit a series of selects, one per component, that gives us 0 or the loaded value depending on whether or not you're in bounds. However, we were hard-coding 4 components which may not be correct. Instead, we should be using size which is the number of components read. Reviewed-by: Francisco Jerez <[email protected]>
* i965/fs: Only read output_components many components when writing an outputJason Ekstrand2015-09-151-1/+3
| | | | Reviewed-by: Kristian Høgsberg <[email protected]>
* i965/fs: Set output_components for lowered clip distance outputsJason Ekstrand2015-09-151-0/+2
| | | | Reviewed-by: Kristian Høgsberg <[email protected]>
* mesa/teximage: restrict GL_ETC1_RGB8_OES support to GLESNanley Chery2015-09-151-1/+2
| | | | | | | | | | | According to the extensions table and our glext headers, OES_compressed_ETC1_RGB8_texture is only supported in GLES1 and GLES2. Since we may give users a GLES3 context when a GLES2 context is requested, we also allow this extension for GLES3 as well. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/extensions: restrict GL_OES_EGL_image to GLESNanley Chery2015-09-151-2/+1
| | | | | | | | Driver vendors do this as well. The extension specification lists GLES 1.1 or 2.0 as requirements. Reviewed-by: Chad Versace <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* mesa/extensions: restrict luminance alpha formats to API_OPENGL_COMPATNanley Chery2015-09-152-4/+6
| | | | | | | According the GL 3.1 spec, luminance alpha formats are deprecated. Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Nanley Chery <[email protected]>
* gallium/svga: Enable PIPE_FORMAT_L8_UNORM for vgpu10Thomas Hellstrom2015-09-151-1/+1
| | | | | | | | It's extensively used by XA for a8- and planar yuv component surfaces. This fixes broken XA yuv blits using vgpu10 contexts. Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* egl/dri2: don't leak the fd on dri2_terminateEmil Velikov2015-09-153-1/+3
| | | | | | | | | | Currently the check was incorrect as it did not consider the (unlikely) case of fd == 0. In order to fix this we should first correctly initialize it to -1, as the swrast implementations leave it set to zero (props to calloc()). Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Boyan Ding <[email protected]>
* egl/dri2/drm: compact existing device mgmtEmil Velikov2015-09-151-6/+4
| | | | | | | | | Move the fcntl(dupfd_cloexec) to the else branch where it belongs. Otherwise it's not immediately obvious that the code is hit, only when an existing device is used. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Boyan Ding <[email protected]>
* egl/dri2: Close file descriptor on error.Matt Turner2015-09-151-13/+14
| | | | | | | | | | v2: [Emil Velikov] Rework the error path to a common goto, close only if we own the fd. v3; [Emil Velikov] Always close the fd (we either opened the device or dup'd) (Boyan, Ian) Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Boyan Ding <[email protected]>
* gbm: convert gbm bo format to fourcc format on dma-buf importRay Strode2015-09-151-1/+17
| | | | | | | | | | | | | | | | | | | | | At the moment if a gbm buffer is imported and the gbm buffer has an old-style GBM_BO_FORMAT format, the import will crash, since it's passed directly to DRI functions that expect a fourcc format (as provided by the newer GBM_FORMAT definitions) This commit addresses the problem in two ways: 1) it prevents invalid formats from leading to a crash by returning EINVAL if the image couldn't be created 2) it translates GBM_BO_FORMAT formats into the comparable GBM_FORMAT formats. Reference: https://bugzilla.gnome.org/show_bug.cgi?id=753531 CC: "10.6 11.0" <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* docs: document INTEL_DEBUG 'optimizer' envvarAlejandro Piñeiro2015-09-151-0/+1
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965: Move perf_debug code to brw_codegen_*_prog()Kristian Høgsberg Kristensen2015-09-145-76/+75
| | | | | | | | | | We're trying to avoid a libdrm dependency in the core compiler, so let's move the perf_debug code one level up from the brw_*_emit() helpers to the brw_codegen_*_prog() helpers. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
* i965: Move brw_fs_precompile() to brw_wm.cKristian Høgsberg Kristensen2015-09-142-58/+59
| | | | | | | | | All other precompile functions live in the brw_<stage>.c files, make fs follow the convention. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Signed-off-by: Kristian Høgsberg Kristensen <[email protected]>
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