summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* meson: Allow building glvnd with EGL and non-dri based GLXDylan Baker2017-11-081-2/+6
| | | | | | | | | | | Because meson mirrors the auototools logic, it needs the same changes to allow building glvnd based egl. v2: - change if to elif (Eric) Signed-off-by: Dylan Baker <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Acked-by: Emil Velikov <[email protected]>
* configure.ac: require xcb* for the omx/va/... when using x11 platformEmil Velikov2017-11-081-1/+3
| | | | | | | | | | | | Targets such as omx and va can work w/o anything X related. Mandate the xcb* dependencies only when the X11 platform is selected. Reported-by: Lukas Rusak <[email protected]> Fixes: 63e11ac2b5c ("configure: error out if building VA w/o supported platform") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Lukas Rusak <[email protected]> (v1)
* configure.ac: loosen --enable-glvnd check to honour eglEmil Velikov2017-11-081-8/+4
| | | | | | | | | | | | | | | Currently we error out when building GLVND w/o GLX. That was the original premice before we had EGL. As the commit says, that error should be reworked to honour both - do so. v2: Drop noop *);; (Eric) Reported-by: Lukas Rusak <[email protected]> Fixes: ce562f9e3fa ("EGL: Implement the libglvnd interface for EGL (v3)") Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]> Tested-by: Lukas Rusak <[email protected]> (v1)
* egl/android: add a note about .swap_buffers_with_damageEmil Velikov2017-11-081-1/+1
| | | | | | | | | | | | | Android implements the API and does the native damage handling itself. At the same time it a) does call the vendor's eglSwapBuffersWithDamageKHR b) does not implement eglSetDamageRegionKHR There's something strange happening here. For now simply note about the 'lack' of eglSwapBuffersWithDamageKHR support. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* wayland-drm: static inline wayland_drm_buffer_getEmil Velikov2017-11-085-43/+39
| | | | | | | | | | | | | | | | | | | | The function is effectively a direct function call into libwayland-server.so. Thus GBM no longer depends on the wayland-drm static library, making the build more straight forward. And the resulting binary is a bit smaller. Note: we need to move struct wayland_drm_callbacks further up, otherwise we'll get an error since the type is incomplete. v2: Rebase, beef-up commit message, update meson, move struct wayland_drm_callbacks. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Daniel Stone <[email protected]> (v1) Reviewed-by: Eric Engestrom <[email protected]> # meson bit only Acked-by: Eric Engestrom <[email protected]> # for the rest Reviewed-by: Dylan Baker <[email protected]> # meson
* automake: intel: correctly append to the LIBADD variableEmil Velikov2017-11-081-1/+1
| | | | | | | | | | | | | | Commit 05fc62d89f5 sets the variable, yet it forgot the update the existing reference to append (instead of assign). Thus as-is the expat library was discarded from the link chain when building with Android. Fixes: 05fc62d89f5 ("automake: intel: move expat handling where it's used") Cc: Hongxu Jia <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* configure: enable the OpenCL ICD by defaultEmil Velikov2017-11-082-2/+3
| | | | | | | | | | | | | | | | | | | | Nearly all the distributions* that build Mesa OpenCL, enable the ICD. Since building a non-ICD driver has the chance of conflicting with existing OpenCL binary (libOpenCL.so). Furthermore, some applications expect the library to provide annotated/versioned symbols. https://lists.freedesktop.org/archives/mesa-dev/2017-September/171093.html *Fedora, Suse, Arch, Debian, Ubuntu, FreeBSD use the ICD Gentoo manages the conflicting files via eselect. Cc: Matt Turner <[email protected]> Cc: Jan Vesely <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-By: Aaron Watry <[email protected]>
* targets/opencl: don't hardcode the icd file install to /etc/...Emil Velikov2017-11-081-1/+1
| | | | | | | | | | | | | | | | Use $(sysconfdir) instead of hardcoding /etc. While the OpenCL spec expects the file in /etc, people building their stack can override that, esp. !Linux users. Furthermore this removes a fundamental violation, which results in the system file being overwritten even as one explicitly sets --prefix and/or DESTDIR. Cc: [email protected] Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Francisco Jerez <[email protected]> Reviewed-By: Aaron Watry <[email protected]>
* amd: add amdgpu_asic_addr.h to the sources listEmil Velikov2017-11-081-0/+1
| | | | | | | Otherwise it will be missing from the release tarball Fixes: 7f33e94e43a ("amd/addrlib: update to latest version") Signed-off-by: Emil Velikov <[email protected]>
* gallivm: Use new LLVM fast-math-flags APITobias Droste2017-11-081-0/+4
| | | | | | | | | | | | | LLVM 6 changed the API on the fast-math-flags: https://reviews.llvm.org/rL317488 NOTE: This also enables the new flag 'ApproxFunc' to allow for approximations for library functions (sin, cos, ...). I'm not completly convinced, that this is something mesa should do. Signed-off-by: Tobias Droste <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-and-Tested-by: Michel Dänzer <[email protected]>
* glsl: add varying resources for arrays of complex typesJuan A. Suarez Romero2017-11-081-4/+59
| | | | | | | | | | | | | This patch is mostly a patch done by Ilia Mirkin. It fixes KHR-GL45.enhanced_layouts.varying_structure_locations. v2: fix locations for TCS/TES/GS inputs and outputs (Ilia) CC: Ilia Mirkin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103098 Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Juan A. Suarez Romero <[email protected]>
* st/glsl_to_nir: use nir_shader_gather_info()Timothy Arceri2017-11-081-8/+10
| | | | | | | | Use the NIR helper rather than the GLSL IR helper to get in/out masks. This allows us to ignore varyings removed by NIR optimisations. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: generate NIR earlierTimothy Arceri2017-11-082-37/+14
| | | | | | | | We want to use nir_shader_gather_info() the GLSL IR version might be including varyings that NIR later eliminates. To do this we need to generate NIR before we we start using the in/out bitmasks. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/glsl_to_nir: delay adding built-in uniforms to Parameters listTimothy Arceri2017-11-082-36/+34
| | | | | | | | Delaying adding built-in uniforms until after we convert to NIR gives us a better chance to optimise them away. Also NIR allows us to iterate over the uniforms directly so should be faster. Reviewed-by: Nicolai Hähnle <[email protected]>
* amd/addrlib: update to latest versionMarek Olšák2017-11-0832-3335/+1354
| | | | | | | | | | | | This uses C++11 initializer lists. I just overwrote all Mesa files with internal addrlib and discarded hunks that we should probably keep, but I might have missed something. The code depending on ADDR_AM_BUILD is removed. We can add it back next time if needed. Acked-by: Nicolai Hähnle <[email protected]>
* braodcom/vc5: Flush the job when it grows over 1GB.Eric Anholt2017-11-073-0/+10
| | | | | Fixes GL_OUT_OF_MEMORY from streaming-texture-leak (and will hopefully keep piglit from ooming on my no-swap platform, as well).
* broadcom/vc5: Do 16-bit unpacking of integer texture returns properly.Eric Anholt2017-11-071-8/+29
| | | | | We were doing f16 unpacks, which trashed "1" values. Fixes many piglit texwrap GL_EXT_texture_integer cases.
* broadcom/vc5: Fix pausing of transform feedback.Eric Anholt2017-11-071-1/+1
| | | | | | Gallium disables it by removing the streamout buffers, not by binding a program that doesn't have TF outputs. Fixes piglit "ext_transform_feedback2/counting with pause"
* broadcom/vc5: Add support for GL_RASTERIZER_DISCARDEric Anholt2017-11-071-0/+2
| | | | Fixes piglit discard-drawarrays.
* broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.Eric Anholt2017-11-072-5/+33
| | | | | | | The v3d_qpu_writes_r*() were only checking for fixed-function accumulator writes, not normal ALU writes to those regs. Fixes fs-discard-exit-2 on simulation (but not HW).
* broadcom/vc5: Add partial transform feedback query support.Eric Anholt2017-11-073-17/+64
| | | | | | We have to compute the queries in software, so we're counting the primitives by hand. We still need to make sure to not increment the PRIMITIVES_EMITTED if we overflowed, but leave that for later.
* broadcom/vc5: Add occlusion query support.Eric Anholt2017-11-077-20/+125
| | | | Fixes all of piglit's OQ tests.
* intel/fs/nir: Return Q types from brw_reg_type_for_bit_sizeJason Ekstrand2017-11-071-2/+2
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/fs/nir: Use Q immediates for load_const on gen8+Jason Ekstrand2017-11-071-3/+11
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/fs/nir: Setup immediates based on type in i2b and f2bJason Ekstrand2017-11-071-1/+2
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* intel/reg: Add helpers for 64-bit integer immediatesJason Ekstrand2017-11-071-0/+18
| | | | Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* compiler/nir_types: Handle vectors in glsl_get_array_elementJason Ekstrand2017-11-071-0/+2
| | | | | | | | | | | Most of NIR doesn't allow doing array indexing on a vector (though it does on a matrix). However, nir_lower_io handles it just fine and this behavior is needed for shared variables in Vulkan. This commit makes glsl_get_array_element do something sensible for vector types and makes nir_validate happy with them. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Validate base types on array dereferencesJason Ekstrand2017-11-071-2/+16
| | | | | | | | | We were already validating that the parent type goes along with the child type but we weren't actually validating that the parent type is reasonable. This fixes that. Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir,intel/compiler: Use a fixed subgroup sizeJason Ekstrand2017-11-074-28/+15
| | | | | | | | | | | | | | | | The GL_ARB_shader_ballot spec says that gl_SubGroupSizeARB is declared as a uniform. This means that it cannot change across an invocation such as a draw call or a compute dispatch. For compute shaders, we're ok because we only ever use one dispatch size. For fragment, however, the hardware dynamically chooses between SIMD8 and SIMD16 which violates the spec. Instead, let's just pick a subgroup size based on the shader stage. The fixed size we choose for compute shaders is a bit higher than strictly needed but there's no real harm in that. The advantage is that, if they do anything interesting with the value, NIR will see it as an immediate and can optimize better. Acked-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir/lower_subgroups: Lower ballot intrinsics to the specified bit sizeJason Ekstrand2017-11-075-31/+84
| | | | | | | | | | | | | | Ballot intrinsics return a bitfield of subgroups. In GLSL and some SPIR-V extensions, they return a uint64_t. In SPV_KHR_shader_ballot, they return a uvec4. Also, some back-ends would rather pass around 32-bit values because it's easier than messing with 64-bit all the time. To solve this mess, we make nir_lower_subgroups take a new parameter called ballot_bit_size and it lowers whichever thing it gets in from the source language (uint64_t or uvec4) to a scalar with the specified number of bits. This replaces a chunk of the old lowering code. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir/builder: Add a nir_imm_intN_t helperJason Ekstrand2017-11-071-0/+12
| | | | | | | This lets you easily build integer immediates of arbitrary bit size. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* nir/lower_system_values: Lower SUBGROUP_*_MASK based on typeJason Ekstrand2017-11-071-2/+3
| | | | | | | | | The SUBGROUP_*_MASK system values are uint64_t when coming in from GLSL but uvec4 when coming in from SPIR-V. Lowering based on type allows us to nicely handle both. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Make ballot intrinsics variable-sizeJason Ekstrand2017-11-073-6/+8
| | | | | | | | This way they can return either a uvec4 or a uint64_t. At the moment, this is a no-op since we still always return a uint64_t. Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add a ssa_dest_init_for_type helperJason Ekstrand2017-11-071-0/+9
| | | | | | | This would be useful a number of places Reviewed-by: Lionel Landwerlin <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* nir: Add a new subgroups lowering passJason Ekstrand2017-11-078-186/+208
| | | | | | | | | | | | This commit pulls nir_lower_read_invocations_to_scalar along with most of the guts of nir_opt_intrinsics (which mostly does subgroup lowering) into a new nir_lower_subgroups pass. There are various other bits of subgroup lowering that we're going to want to do so it makes a bit more sense to keep it all together in one pass. We also move it in i965 to happen after nir_lower_system_values to ensure that because we want to handle the subgroup mask system value intrinsics here. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Don't use automatic exec size inferenceJason Ekstrand2017-11-071-3/+9
| | | | | | | | | | | | | | The automatic exec size inference can accidentally mess things up if we're not careful. For instance, if we have add(4) g38.2<4>D g38.1<8,2,4>D g38.2<8,2,4>D then the destination register will end up having a width of 2 with a horizontal stride of 4 and a vertical stride of 8. The EU emit code sees the width of 2 and decides that we really wanted an exec size of 2 which doesn't do what we wanted. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-074-9/+15
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/eu: Explicitly set EXECUTE_1 where neededJason Ekstrand2017-11-071-0/+9
| | | | Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/eu: Make automatic exec sizes a configurable optionJason Ekstrand2017-11-073-14/+29
| | | | | | | | | | | | | | We have had a feature in codegen for some time that tries to automatically infer the execution size of an instruction from the width of its destination. For things such as fixed function GS, clipper, and SF programs, this is very useful because they tend to have lots of hand-rolled register setup and trying to specify the exec size all the time would be prohibitive. For things that come from a higher-level IR, however, it's easier to just set the right size all the time and the automatic exec sizes can, in fact, cause problems. This commit makes it optional while enabling it by default. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Rework zero-length URB write handlingJason Ekstrand2017-11-071-29/+31
| | | | | | | | | | | | | | Originally we tried to handle this case based on slots_valid. However, there are a number of ways that this can go wrong. For one, we throw away any trailing slots which either aren't written or are set to VARYING_SLOT_PAD. Second, even if PSIZ is a valid slot, we may not actually write anything there. Between the lot of these, it was possible to end up in a case where we tried to do a regular URB write but ended up with a length of 1 which is invalid. This commit moves it to the end and makes it based on a new boolean flag urb_written. Reviewed-by: Iago Toral Quiroga <[email protected]> Cc: [email protected]
* intel/compiler/fs: Set up subgroup invocation as a system valueJason Ekstrand2017-11-071-13/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Subgroup invocation is computed using a vector immediate and some dispatch-aware arithmetic. Unfortunately, due to the vector arithmetic, and the fact that it's frequently read 16-wide, it's not something that can easily be CSEd by the back-end compiler. There are a few different possible approaches to this problem: 1) Emit the code to calculate the subgroup invocation on-the-fly and trust NIR to do the CSE. This is what we were doing. 2) Add a back-end instruction for the subgroup ID. This has the advantage of helping the back-end compiler with CSE but has the downside of very poor scheduling for the calculation because it has to be emitted in the back-end. 3) Emit the calculation at the top of the program and re-use the result. This gets rid of the CSE problem but comes at the cost of an extra live register. This commit switches us from 1) to 3). We choose to store the subgroup invocation values as a W type to reduce the impact of the extra live register. Trusting NIR and using 1) was fine but we're soon going to want to use the subgroup invocation value for other things in the back-end compiler and this makes it much easier to do without having to worry about CSE problems. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/cs: Push subgroup ID instead of base thread IDJason Ekstrand2017-11-079-36/+40
| | | | | | | | | | We're going to want subgroup ID for SPIR-V subgroups eventually anyway. We really only want to push one and calculate the other from it. It makes a bit more sense to push the subgroup ID because it's simpler to calculate and because it's a real API thing. The only advantage to pushing the base thread ID is to avoid a single SHL in the shader. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/cs: Re-run final NIR optimizations for each SIMD sizeJason Ekstrand2017-11-071-41/+69
| | | | | | | | | | | | With the advent of SPIR-V subgroup operations, compute shaders will have to be slightly different depending on the SIMD size at which they execute. In order to allow us to do dispatch-width specific things in NIR, we re-run the final NIR stages for each sIMD width. One side-effect of this change is that we start rallocing fs_visitors which means we need DECLARE_RALLOC_CXX_OPERATORS. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/compiler: Move the destructor from vec4_visitor to backend_shaderJason Ekstrand2017-11-074-5/+5
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965/fs: Get rid of the early return in brw_compile_csJason Ekstrand2017-11-071-13/+14
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* intel/cs: Rework the way thread local ID is handledJason Ekstrand2017-11-076-46/+32
| | | | | | | | | | Previously, brw_nir_lower_intrinsics added the param and then emitted a load_uniform intrinsic to load it directly. This commit switches things over to use a specific NIR intrinsic for the thread id. The one thing I don't like about this approach is that we have to copy thread_local_id over to the new visitor in import_uniforms. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/fs: Mark 64-bit values as being contiguousJason Ekstrand2017-11-071-1/+4
| | | | | | | | | | | This isn't often a problem , when we're in a compute shader, we must push the thread local ID so we decrement the amount of available push space by 1 and it's no longer even and 64-bit data can, in theory, span it. By marking those uniforms contiguous, we ensure that they never get split in half between push and pull constants. Reviewed-by: Iago Toral Quiroga <[email protected]> Cc: [email protected]
* intel/cs: Ignore runtime_check_aads_emit for CSJason Ekstrand2017-11-071-2/+1
| | | | | | It's only set on gen4-5 which clearly don't support compute shaders. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/cs: Stop setting dispatch_grf_start_regJason Ekstrand2017-11-072-3/+0
| | | | | | Nothing ever reads it for compute shaders because it's always 1. Reviewed-by: Iago Toral Quiroga <[email protected]>
* intel/cs: Drop max_dispatch_width checks from compile_csJason Ekstrand2017-11-071-4/+8
| | | | | | | | The only things that adjust fs_visitor::max_dispatch_width are render target writes which don't happen in compute shaders so they're pointless. Reviewed-by: Iago Toral Quiroga <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-26 06:15:46 +0000