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* radeonsi: clean up decompress blend state namesMarek Olšák2017-06-074-10/+10
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: clean up a misleading statement from the old daysMarek Olšák2017-06-071-4/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: don't use 1D tiling for Z/S on VI to get TC-compatible HTILEMarek Olšák2017-06-071-3/+13
| | | | | | It's always good to have fewer decompress blits. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: enable TC-compatible stencil compression on VIMarek Olšák2017-06-073-5/+8
| | | | | | | Most things are in place. Ideally we won't see decompress blits for stencil anymore. Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: don't keep framebuffer state in st_contextMarek Olšák2017-06-077-51/+48
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: cache pipe_surface for GL_FRAMEBUFFER_SRGB changesMarek Olšák2017-06-074-29/+41
| | | | | Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* st/mesa: use gl_driver_flags::NewFramebufferSRGBMarek Olšák2017-06-071-3/+6
| | | | | | | also call st_init_driver_flags when st_context is initialized. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: add gl_driver_flags::NewFramebufferSRGBMarek Olšák2017-06-072-1/+7
| | | | | | | _NEW_BUFFERS updates too much stuff. Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: prevent a race when the previous shader's main part is missingMarek Olšák2017-06-071-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: wait for main part compilation of 1st shaders of merged shadersMarek Olšák2017-06-071-0/+4
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi/gfx9: fix LS scratch buffer support without TCS for GFX9Marek Olšák2017-06-071-3/+18
| | | | | | | | | | LS is merged into TCS. If there is no TCS, LS is merged into fixed-func TCS. The problem is the fixed-func TCS was ignored by scratch update functions, so LS didn't have the scratch buffer set up. Note that Mesa 17.1 doesn't have merged shaders. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move streamout state update out of si_update_shadersMarek Olšák2017-06-072-16/+25
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: remove dead code in declare_input_fsMarek Olšák2017-06-071-5/+0
| | | | | | Colors are interpolated in the PS prolog. This was never used. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: move handling of DBG_NO_OPT_VARIANT into si_shader_selector_keyMarek Olšák2017-06-071-4/+3
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: use a compiler queue with a low priority for optimized shadersMarek Olšák2017-06-073-8/+34
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* util/u_queue: add an option to set the minimum thread priorityMarek Olšák2017-06-078-8/+29
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: decrease the number of compiler threads to num CPUs - 1Marek Olšák2017-06-071-1/+4
| | | | | | Reserve one core for other things (like draw calls). Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: drop unfinished shader compilations when destroying shadersMarek Olšák2017-06-072-3/+5
| | | | | | | If we enqueue too many jobs and destroy the GL context, it may take several seconds before the jobs finish. Just drop them instead. Reviewed-by: Nicolai Hähnle <[email protected]>
* util/u_queue: add a way to remove a job when we just want to destroy itMarek Olšák2017-06-072-6/+49
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* freedreno/a5xx: set SP_BLEND_CONTROL properlyRob Clark2017-06-073-1/+4
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: LRZ supportRob Clark2017-06-0714-14/+234
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: drop timestamp fieldRob Clark2017-06-072-3/+0
| | | | | | unused. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a5xx: refactor out helper for LRZ flushRob Clark2017-06-073-11/+19
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: reshuffle FD_MESA_DEBUG bitmaskRob Clark2017-06-071-3/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: update generated headersRob Clark2017-06-077-17/+31
| | | | Signed-off-by: Rob Clark <[email protected]>
* gallium/u_blitter: use 2D_ARRAY for cubemap blits if possibleMarek Olšák2017-06-075-22/+39
| | | | | | | | so that we can use TXF. The cubemap blit pixel shader code size: 148 -> 92 bytes Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_blitter: use TXF if possibleMarek Olšák2017-06-071-102/+190
| | | | | | | | | | | | | | | | | | This fixes piglit: arb_texture_view-rendering-r32ui TEX (image_sample) flushes denorms to 0 with FP32 textures on GCN, but such a texture can contain integer data written using an integer render view. If we do a transfer blit with TEX, denorms are flushed to 0. Luckily, TXF (image_load) doesn't do that. TXF also doesn't need to load the sampler state, so blit shaders don't have to do s_load_dwordx4. TXF doesn't do CLAMP_TO_EDGE, so it can only be used if the src box is in bounds, or if we clamp manually (this commit doesn't). Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/u_blitter: use TEX_LZ if it's supportedMarek Olšák2017-06-071-4/+8
| | | | | | | The sampler views always have first_level == last_level. Now radeonsi doesn't have to use the WQM. (a few SALU removed) Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/util: add _LZ and TXF options to simple shadersMarek Olšák2017-06-076-33/+77
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/ureg: add TEX/TXF_LZ opcodes to uregMarek Olšák2017-06-071-0/+2
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* i965: Use BLORP for all HiZ opsJason Ekstrand2017-06-073-162/+10
| | | | | | | | BLORP has been capable of doing gen8-style HiZ ops for a while now. We might as well start using it. The one downside is that this may cause a bit more state emission since we still re-emit most things for BLORP. Reviewed-by: Topi Pohjolainen <[email protected]>
* blorp: Use FullSurfaceDepthandStencilClear for blorp_hiz_opJason Ekstrand2017-06-073-0/+5
| | | | | | | The blorp_hiz_op entrypoint always acts on a full subresource of a HiZ buffer so we can just set the flag unconditionally. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move the post-HiZ-clear flush/stall to intel_hiz_execJason Ekstrand2017-06-072-16/+18
| | | | | | | | This also changes it to be predicated so we only do the flush/stall on clears and HiZ resolves. The docs only say it's needed for clears but empirical evidence says it's also needed for HiZ resolves. Reviewed-by: Topi Pohjolainen <[email protected]>
* intel/blorp: Plumb through access to the workaround BOJason Ekstrand2017-06-073-2/+32
| | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101283 Reviewed-by: Topi Pohjolainen <[email protected]>
* anv/blorp: Move the depth cache flush outside of BLORPNanley Chery2017-06-072-8/+16
| | | | | Signed-off-by: Nanley Chery <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/blorp: Refactor the HiZ op interfaceJason Ekstrand2017-06-074-55/+60
| | | | | | | | | | This commit does a few things: 1) Now that BLORP can do HiZ ops on gen8+, drop the gen6 prefix. 2) Switch parameters to uint32_t to match the rest of blorp. 3) Take a range of layers and loop internally. Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Inline gen6_blorp_execJason Ekstrand2017-06-071-18/+11
| | | | Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Perform HiZ flush/stall prior to HiZ resolvesJason Ekstrand2017-06-071-13/+26
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965: Move the pre-depth-clear flush/stalls to intel_hiz_execJason Ekstrand2017-06-072-56/+58
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Take a layer range in intel_hiz_execJason Ekstrand2017-06-075-18/+16
| | | | | Cc: "17.1" <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/miptree: Store fast clear colors in an isl_color_valueJason Ekstrand2017-06-0715-137/+91
| | | | | | | | | | | | | | | | | | | | | | | | This commit, out of necessity, makes a number of changes at once: 1) Changes intel_mipmap_tree to store the clear color for both color and depth as an isl_color_value. 2) Changes the depth/stencil emit code to do the format conversion of the depth clear value on Haswell and earlier instead of pulling a uint32_t directly from the miptree. 3) Changes ISL's depth/stencil emit code to perform the format conversion of the depth clear value on Haswell and earlier instead of assuming that the depth value in the float is pre-converted. 4) Changes blorp to pass the depth value through as a float. 5) Changes the Vulkan driver to pass the depth value to blorp as a float rather than a uint. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* dri3/GLX: Fix drawable invalidation v2Thomas Hellstrom2017-06-071-0/+6
| | | | | | | | | | | | | | | | | | | A number of internal VMware apitrace traces image comparisons fail with dri3 because the viewport transformation becomes incorrect after an X drawable resize. The incorrect viewport transformation sometimes persist until the second draw-call after a swapBuffer. Comparing with the dri2 glx code there are a couple of places where dri2 invalidates the drawable in the absence of server-triggered invalidation, where dri3 doesn't do that. When these invalidation points are added to dri3, the image comparisons become correct. v2: Addressed review comment by Michel Dänzer. Cc: <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]> Reviewed-and-tested-by: Michel Dänzer <[email protected]>
* i965: Fix alpha to one with dual color blending.Kenneth Graunke2017-06-071-13/+44
| | | | | | | | | | | | | | | | | | | The BLEND_STATE documentation says that alpha to one must be disabled when dual color blending is enabled. However, it appears that it simply fails to override src1 alpha to one. We can work around this by leaving alpha to one enabled, but overriding SRC1_ALPHA to ONE and ONE_MINUS_SRC1_ALPHA to ZERO. This appears to be what the other driver does, and it looks like it works despite the documentation saying not to do it. Fixes spec/ext_framebuffer_multisample/alpha-to-one-dual-src-blend * Piglit tests. v2: Add UNUSED to shut up warning on generations which don't use this. Reviewed-by: Chris Forbes <[email protected]> Reviewed-by: Anuj Phogat <[email protected]>
* mesa: add KHR_no_error support for glTexSubImage*D()Samuel Pitoiset2017-06-073-3/+64
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add texsubimage() helperSamuel Pitoiset2017-06-071-0/+18
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: make _mesa_texture_sub_image() staticSamuel Pitoiset2017-06-071-20/+20
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: rename texsubimage() to texsubimage_err()Samuel Pitoiset2017-06-071-17/+17
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add KHR_no_error support for glCopyImageSubData()Samuel Pitoiset2017-06-073-1/+31
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add copy_image_subdata() helperSamuel Pitoiset2017-06-071-31/+45
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* mesa: add prepare_target() helperSamuel Pitoiset2017-06-071-0/+24
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>