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* broadcom/vc5: Use MSF to ignore discards/non-dispatched channels in loops.Eric Anholt2018-01-121-1/+5
| | | | | Prevents potential infinite loops when a non-dispatched or discarded channel never triggers the loop break condition.
* broadcom/vc5: Use XOR instead of SUB for execute flags comparisons.Eric Anholt2018-01-121-3/+3
| | | | | I think this should be equivalent other than power, and it's the kind of comparison we use for nir_op_ieq.
* broadcom/vc5: Also check the update flags for avoiding DCE.Eric Anholt2018-01-121-1/+5
| | | | I was trying to do a NULL-destination UF, and it got removed.
* broadcom/vc5: Fix up channel swizzling for textures on 4.x.Eric Anholt2018-01-121-2/+5
| | | | | | | | I had 3.x putting swizzling in the texture state only for 16-bit texture returns, and in the shader for 32-bit. This may be due to having mixed up the return channel setup on 3.x back before I had moved it into the compiler. On 4.x, the non-border-color texwrap tests are passing nicely with both 16 and 32-bit returns with swizzling in the texture state.
* broadcom/vc5: Port the draw-time state emission to V3D 4.1.Eric Anholt2018-01-127-27/+76
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* broadcom/vc5: Rename V3D 3.x Flat Shade Action to match v4.x naming.Eric Anholt2018-01-122-8/+8
| | | | | Now that the actions are reused for centroid and nonperspective, give them a more generic name.
* broadcom/vc5: Update pixel center setup for V3D 4.x.Eric Anholt2018-01-121-2/+12
| | | | | The fxcd/fycd instructions now return half-integer pixel centers when not doing sample-rate shading.
* broadcom/vc5: Print the buffer name in simulator overflow checks.Eric Anholt2018-01-121-2/+4
| | | | Revealed that I was writing past the TSDA, not the Z buffer as I expected.
* broadcom/vc5: Add support for loading varyings in V3D 4.1.Eric Anholt2018-01-126-17/+13
| | | | | | | The LDVARY signal now writes an arbitrary register, so I took out the magic src register file and replaced it with an instruction with LDVARY set so we have somewhere to hang a QFILE_TEMP destination for register allocation.
* broadcom/vc5: Update state setup for V3D 4.1.Eric Anholt2018-01-127-14/+206
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* broadcom/vc5: Add compiler support for V3D 4.x texturing.Eric Anholt2018-01-127-6/+283
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* broadcom/vc5: Add the new TMU write addresses for V3D 4.x (and r5rep).Eric Anholt2018-01-122-10/+37
| | | | | | The V3D 3.x series of TMU writes with meaning depending on the texture type is replaced with writes to specific registers for each texture argument semantic.
* broadcom/vc5: Move V3D 3.3 texturing to a separate file.Eric Anholt2018-01-125-229/+267
| | | | | V3D 4.x texturing changes enough that #ifdefs would just make a mess of it.
* broadcom/vc5: Move V3D 3.3 VPM write setup to a separate file.Eric Anholt2018-01-125-34/+82
| | | | | For V4.1 texturing, I need the V4.1 XML, so the main compiler needs to stop including V3.3 XML.
* broadcom/vc5: Set up depth formats for V3D 4.x.Eric Anholt2018-01-121-1/+12
| | | | | We no longer have the small depth-specific output format enum, and instead depth is just at the end of the output image format enum.
* broadcom/vc5: Always use the RGBA8 formats for RGBX8.Eric Anholt2018-01-121-3/+7
| | | | | The RGBX8 formats were dropped from V3D 4.x, but we don't really need them anyway (we already handle other non-alpha formats by forcing A to 1).
* broadcom/vc5: Move the formats table to per-V3D-version compile.Eric Anholt2018-01-1212-337/+451
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* broadcom/vc5: Add support for V3D 4.1 CLIF dumping.Eric Anholt2018-01-125-17/+57
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* broadcom/vc5: Move the body of CLIF dumping to a per-version file.Eric Anholt2018-01-126-155/+255
| | | | | I want the library's entrypoints to still be unversioned, but the actual packet dumping needs to be per-version.
* broadcom/vc5: Use THRSW to enable multi-threaded shaders.Eric Anholt2018-01-129-81/+311
| | | | | This is a major performance boost on all of V3D, but is required on V3D 4.x where shaders are always either 2- or 4-threaded.
* broadcom/vc5: Properly schedule the thread-end THRSW.Eric Anholt2018-01-122-39/+137
| | | | | | | | | | This fills in the delay slots of thread end as much as we can (other than being cautious about potential TLBZ writes). In the process, I moved the thread end THRSW instruction creation to the scheduler. Once we start emitting THRSWs in the shader, we need to schedule the thread-end one differently from other THRSWs, so having it in there makes that easy.
* broadcom/vc5: Implement GFXH-1684 workaround.Eric Anholt2018-01-124-0/+20
| | | | Apparently the VPM writes need to be flushed out before we end the shader.
* broadcom/vc5: Port drawing commands to V3D 4.x.Eric Anholt2018-01-129-20/+93
| | | | | This required extending the CL submit ioctl, because the tile alloc/state buffer setup has moved from the BCL to register writes.
* broadcom/vc5: Add a test for .ifb in ADD ops.Eric Anholt2018-01-121-0/+1
| | | | | I had a .ifb being decoded weird in sampid, so this is to check that .ifb is fine.
* broadcom/vc5: Add the new tesselation opcodes in V3D 4.1.Eric Anholt2018-01-122-1/+5
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* broadcom/vc5: Use a physical-reg-only register class for LDVPM.Eric Anholt2018-01-122-8/+21
| | | | | This is needed for LDVPM on V3D 4.x, but will also be needed for keeping values out of the accumulators across THRSW.
* broadcom/vc5: Use the new LDVPM/STVPM opcodes on V3D 4.1.Eric Anholt2018-01-129-51/+197
| | | | | | | | | | | Now, instead of a magic write register for VPM stores we have an instruction to do them (which means no packing of other ALU ops into it), with the ability to reorder the VPM stores due to the offset being baked into the instruction. VPM loads also gain the ability to be reordered by packing the row into the A argument. They also no longer write to the r3 accumulator, and instead must be stored to a physical register.
* broadcom/vc5: Drop dead VC5_QPU_* defines from qpu_instr.c.Eric Anholt2018-01-121-80/+0
| | | | | I had all the packing code in this file at one point, but these defines now live in qpu_pack.c.
* broadcom/vc5: Add support for QPU pack/unpack/disasm of small immediates.Eric Anholt2018-01-124-1/+94
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* broadcom/vc5: Enable the driver on V3D 4.1Eric Anholt2018-01-121-1/+1
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* broadcom/vc5: Port the simulator to support V3D 4.1Eric Anholt2018-01-129-125/+216
| | | | | | | This required moving the register accesses to a separate v3dx file, since the register definitions for each V3D version collide. It seems that initializing the v3d_hw from a file dictating 3.3 (v3d_simulator_wrapper.cpp) is safe, though.
* broadcom/vc5: Drop signal bit #defines.Eric Anholt2018-01-122-8/+0
| | | | Signals are more complicated than that, and tables ended up being better.
* broadcom/vc5: Add support for V3Dv4 signal bits.Eric Anholt2018-01-1212-45/+322
| | | | | | | The WRTMUC replaces the implicit uniform loads in the first two texture instructions. LDVPM disappears in favor of an ALU op. LDVARY, LDTMU, LDTLB, and LDUNIF*RF now write to arbitrary registers, which required passing the devinfo through to a few more functions.
* broadcom/vc5: Fix pack/unpack of vfmul input unpack flags.Eric Anholt2018-01-122-0/+40
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* broadcom/vc5: Port the RCL setup to V3D4.1.Eric Anholt2018-01-127-58/+360
| | | | | | | The TLB load/store path is rebuilt in this version. There is no longer a single-byte resolved store or the 3-byte extended store. Instead, you get to always use general loads/stores (which, honestly, was tempting even in previous versions).
* broadcom/vc5: Fix per-tile extra clear packet.Eric Anholt2018-01-121-1/+1
| | | | | I accidentally emitted this into the RCL instead of the per-tile generic list, so we wouldn't get tiles after the first cleared.
* broadcom/vc5: Move the TLB loads and stores to helper functions.Eric Anholt2018-01-121-35/+50
| | | | | This is going to get more complicated with V3D 4.1 support, which redoes all the TLB packets.
* broadcom/vc5: Convert vc5_cl.h to use the V3DX() macros.Eric Anholt2018-01-127-10/+24
| | | | | | To conditionally compile cl_emit() macros per V3D version, we need it to expand to whatever V3D we're building for. This required emitting #define V3D_VERSION 33 in all our currently 3.3-only code.
* broadcom/vc5: Introduce v3dx_macros.h and v3dx_pack.h headers.Eric Anholt2018-01-123-1/+88
| | | | | This will be used by vc5 for prefixing functions and including the pack header in v3d-version-dependent code, following the model of anv.
* broadcom/cle: Fix error path of missing a "type" in the XML.Eric Anholt2018-01-121-1/+2
| | | | | | We try to emit a #error and continue so that you can debug the missing type at C compile time, but were missing a couple of definitions in that path (sigh, python).
* broadcom/vc5: Add XML for V3D v4.1 (BCM7278)Eric Anholt2018-01-123-1/+1054
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* ac: add 'const' qualifiers to the shader info passSamuel Pitoiset2018-01-122-8/+11
| | | | | | | For clarification purposes. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* ac: remove unused ac_nir_compiler_options from gather_info_input_decl()Samuel Pitoiset2018-01-121-4/+2
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: add a 'const' qualifier to nir_ssa_def_components_read()Samuel Pitoiset2018-01-122-2/+2
| | | | | | | | To avoid compilation warnings and because this helper shouldn't update anything. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* loader/dri3: Avoid freeing renderbuffers in useThomas Hellstrom2018-01-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Upon reception of an event that lowered the number of active back buffers, the code would immediately try to free all back buffers with an id equal to or higher than the new number of active back buffers. However, that could lead to an active or to-be-active back buffer being freed, since the old number of back buffers was used when obtaining an idle back buffer for use. This lead to crashes when lowering the number of active back buffers by transitioning from page-flipping to non-page-flipping presents. Fix this by computing the number of active back buffers only when trying to obtain a new back buffer. Fixes: 15e208c4cc ("loader/dri3: Don't accidently free buffer holding new back content") Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104214 Cc: "17.3" <[email protected]> Tested-by: Andriy.Khulap <[email protected]> Tested-by: Vadym Shovkoplias <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Thomas Hellstrom <[email protected]>
* anv: VkDescriptorSetLayoutBinding can have descriptorCount == 0Samuel Iglesias Gonsálvez2018-01-121-1/+3
| | | | | | | | | | | | | | | | | From Vulkan spec: "descriptorCount is the number of descriptors contained in the binding, accessed in a shader as an array. If descriptorCount is zero this binding entry is reserved and the resource must not be accessed from any stage via this binding within any pipeline using the set layout." Fixes: dEQP-VK.binding_model.descriptor_update.empty_descriptor.uniform_buffer Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Cc: [email protected]
* mesa: require at least 14 UBOs for GL 4.3Roland Scheidegger2018-01-121-0/+1
| | | | | | | | | | | | ARB_ubo requires 12 UBOs (per stage) at least, but this limit has been raised by GL 4.3 to 14, so don't advertize GL 4.3 without it (only checking the vertex stage since all drivers probably have the same limit anyway for other stages). (piglit has minmax tests for that kind of thing, but they go only up to 3.3, so this won't really be noticed.) I think this currently should not affect any driver - r600 until very recently only supported 12 but now advertizes 14 too. Reviewed-by: Brian Paul <[email protected]>
* util: fix NORETURN for msvc, add HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.hRoland Scheidegger2018-01-122-4/+9
| | | | | | | | | | We've seen some problems internally due to macro redefinition. Fix this by adding HAVE_FUNC_ATTRIBUTE_NORETURN to c99_compat.h, and defining it for msvc. And avoid redefinition just in case. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* radv: don't emit unneeded vertex state.Dave Airlie2018-01-122-8/+49
| | | | | | | | | | | | | | | | | | If the number of instances hasn't changed and we've already emitted it, don't emit it again. If the vertex shader is the same and the first_instance, vertex_offset haven't changed don't emit them again. This increases the fps in GL_vs_VK -t 1 -m -api vk from around 40 to around 60 here, it may not impact anything else. Dieter also reported smoketest going from 1060->1200 fps. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Tested-by: Dieter Nützel <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: trim buffer load result (fixes dota2)Dave Airlie2018-01-121-1/+1
| | | | | | | | | | | Running dota2 since the below commit crashes with an llvm assert. Trim the vector like the other user. This possible could also be avoided by not padding inside the load vec3->vec4. Fixes: 41c36c4549 (amd/common: use ac_build_buffer_load() for emitting UBO loads) Reviewed-by: Samuel Pitoiset <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
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