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* nvc0: bsp_bo can't be nullIlia Mirkin2016-01-171-1/+1
| | | | | | | We already deref it earlier. And these are all allocated on load. Spotted by Coverity. Signed-off-by: Ilia Mirkin <[email protected]>
* llvmpipe: fix arguments order given to vec_andcOded Gabbay2016-01-172-1/+7
| | | | | | | | | | | | | | | | This patch fixes a classic "confuse the enemy" bug. _mm_andnot_si128 (SSE) and vec_andc (VMX) do the same operation, but the arguments are opposite. _mm_andnot_si128 performs "r = (~a) & b" while vec_andc performs "r = a & (~b)" To make sure this error won't return in another place, I added a wrapper function, vec_andnot_si128, in u_pwr8.h, which makes the swap inside. Signed-off-by: Oded Gabbay <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* freedreno/ir3: fix mad 3rd src delay calcRob Clark2016-01-171-1/+1
| | | | | | | In fad158a0 ("freedreno/ir3: array rework") the src # (n) shifted by one, but missed updating delay-slot calc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: better array register allocationRob Clark2016-01-162-9/+51
| | | | | | | Detect arrays which don't conflict with each other and allow overlapping register allocation. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: array offset can be negativeRob Clark2016-01-165-12/+13
| | | | | | | | | | | | | | | | | | | | | | It at least happens with some piglit tests, like $piglit/bin/vp-address-01 VERT DCL IN[0] DCL IN[1] DCL OUT[0], POSITION DCL OUT[1], COLOR DCL CONST[0..7] DCL ADDR[0] 0: ARL ADDR[0].x, IN[1].xxxx 1: MOV_SAT OUT[1], CONST[ADDR[0].x-1] 2: DP4 OUT[0].x, CONST[4], IN[0] 3: DP4 OUT[0].y, CONST[5], IN[0] 4: DP4 OUT[0].z, CONST[6], IN[0] 5: DP4 OUT[0].w, CONST[7], IN[0] 6: END Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: workaround bug/featureRob Clark2016-01-161-0/+9
| | | | | | | | | | Seems like in certain cases, we cannot use c<a0.x+0> as the third src to cat3 instructions. This may be slightly conservative, we may only have this restriction when the first src is also const. This fixes, for example, +24/-0 of the variable-indexing piglit tests. Signed-off-by: Rob Clark <[email protected]>
* ttn: use writemask for store_varRob Clark2016-01-161-26/+2
| | | | | | | Only user is freedreno, and after array-rework it can cope. Avoids generating loads for a store. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: array reworkRob Clark2016-01-169-363/+365
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: refactor/simplify cpRob Clark2016-01-161-87/+82
| | | | | | | | | If we handle separately the special case of eliminating output mov (which includes keeps and various other cases where we don't have a consuming instruction's src register to collapse things into), we can simplify the logic. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix incorrect decoding of mov instructionsRob Clark2016-01-161-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove unused tgsi tokens ptrRob Clark2016-01-161-1/+0
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: bit of ra refactorRob Clark2016-01-161-25/+20
| | | | | | | Shuffle things slightly, passing instr-data to ra_name() to reduce the number of places where we need to add support for array names. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cosmetic de-indentRob Clark2016-01-161-36/+34
| | | | | | Collapse two nested if's into one to reduce indent level. Signed-off-by: Rob Clark <[email protected]>
* ttn: add missing writemask on store_outputRob Clark2016-01-161-0/+1
| | | | | Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir/print: const_index is signedRob Clark2016-01-161-1/+1
| | | | | | | Noticed this with $piglit/bin/vp-address-01 Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: few missing struct namesRob Clark2016-01-161-3/+3
| | | | | | | | | | | | | nir.h is a bit inconsistent about 'typedef struct {} nir_foo' vs 'typedef struct nir_foo {} nir_foo'. But missing struct name tags is inconvenient when you need a fwd declaration without pulling in all of nir. So add missing struct name tag for nir_variable, and a couple other spots where it would likely be useful. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]>
* nv50/ir: add saturate support on ex2Ilia Mirkin2016-01-162-0/+6
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* gallivm: avoid crashing in mod by 0 with llvmpipeJeff Muizelaar2016-01-161-2/+16
| | | | | | | This adds code that is basically the same as the code in umod, udiv and idiv. However, unlike idiv we return -1. Reviewed-by: Roland Scheidegger <[email protected]>
* glsl: Allow implicit int -> uint conversions for bitwise operators (&, ^, |).Kenneth Graunke2016-01-151-8/+38
| | | | | | | | | | | | | | | | | | The ARB has decided that implicit conversions should be performed for bitwise operators in future language revisions. Implementations of current language revisions may or may not perform them. This patch makes Mesa apply implicti conversions even on current language versions. Applications appear to expect this behavior, and there's really no downside to doing so. Fixes shader compilation in Shadow of Mordor. Bugzilla: https://www.khronos.org/bugzilla/show_bug.cgi?id=1405 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Cc: [email protected]
* i965/fs: Always set channel 2 of texture headers in some stagesJason Ekstrand2016-01-151-0/+8
| | | | | | | | | | | | | | | | In the vertex and fragment stages, the hardware is nice to us and leaves g0.2 zerod out for us so we can use it for headers. However, in compute, geometry, and tessellation stages, the hardware is not so nice. In particular, for compute shaders on BDW, the hardware places some debug bits in 23:15. As it happens, bit 15 is interpreted by the sampler as the alpha channel mask. This means that if you use a texturing instruction with a header in a compute shader, you may randomly get the alpha channel disabled. Since channel masks affect the return length of the sampler message, this can lead the GPU to expect a different mlen to the one you specified in the shader and this, in turn, hangs your GPU. Cc: "11.1" <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965/fs/generator: Take an actual shader stage rather than a stringJason Ekstrand2016-01-157-11/+14
| | | | | | Cc: "11.1" <[email protected]> Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/vec4: Use UW type for multiply into accumulator on GEN8+Jason Ekstrand2016-01-151-1/+5
| | | | | | | | BDW adds the following restriction: "When multiplying DW x DW, the dst cannot be accumulator." Cc: "11.1,11.0" <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* llvmpipe: ditch additional ref counting for vertex/geometry sampler viewsRoland Scheidegger2016-01-154-46/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | The cleaning up was quite a performance hog (making pipe_resource_reference the number two in profilers on the vertex path, and 3rd overall, with its cousin pipe_reference_described not far behind) if there were lots of tiny draw calls (ipers). Now the reason was really that it was blindly calling this for all potential shader views (so 32 each for vs and gs) even though the app never touched a single one which could have been fixed, however I can't come up with a good reason why we refcount these. We've got references, of course, in the sampler views, which should be quite sufficient as we do all vertex and geometry shader execution fully synchronous. (Calling prepare_shader_sampling for all draw calls even if there were no changes looks quite suboptimal too, but generally we don't really expect vs/gs shader sampling to be used much with llvmpipe, and there's even an early exit if there aren't any views to avoid the "null loop" albeit it's now no longer always trying to loop through all 32 slots. Maybe improve another time...). Of course, if we manage to make vertex loads run asynchronously some day, we need references again, but adding that back would be the least of the problems... Also only set LP_NEW_SAMPLER_VIEW for fragment sampler views. Nothing on the vertex side depends on it (I suppose we'd really wanted a separate flag in any case). (Good for a 3% improvement or so in ipers under the right conditions.) Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix "leaking" texturesRoland Scheidegger2016-01-152-2/+9
| | | | | | | | | | | | | | | | | | | | | This was not really a leak per se, but we were referencing the textures for longer than intended. If textures were set via llvmpipe_set_sampler_views() (for fs) and then picked up by lp_setup_set_fragment_sampler_views(), they were referenced in the setup state. However, the only way to unreference them was by replacing them with another texture, and not when the texture slot was replaced with a NULL sampler view. (They were then further also referenced by the scene too which might have additional minor side effects as we limit the memory size which is allowed to be referenced by a scene in a rather crude way.) Only setup destruction (at context destruction time) then finally would get rid of the references. Fix this by noting the number of textures the last time, and unreference things if the new view is NULL (avoiding having to unreference things always up to PIPE_MAX_SHADER_SAMPLER_VIEWS which would also have worked). Found by code inspection, no test... v2: rename var Reviewed-by: Jose Fonseca <[email protected]>
* glsl: restrict consumer stage condition to modify interpolation typeSamuel Iglesias Gonsálvez2016-01-151-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Only modify interpolation type for integer-based varyings or when the consumer is known and different than fragment shader. If we are linking separate shader programs and the consumer is unknown, the consumer could be added later and be a fragment shader. If we modify the interpolation type in this case, we could read wrong values in the fragment shader inputs, as shown in bug 93320. Fixes the following CTS test: ES31-CTS.vertex_attrib_binding.advanced-bindingUpdate Fixes the following dEQP tests: dEQP-GLES31.functional.separate_shader.random.102 dEQP-GLES31.functional.separate_shader.random.111 dEQP-GLES31.functional.separate_shader.random.115 dEQP-GLES31.functional.separate_shader.random.17 dEQP-GLES31.functional.separate_shader.random.22 dEQP-GLES31.functional.separate_shader.random.23 dEQP-GLES31.functional.separate_shader.random.3 dEQP-GLES31.functional.separate_shader.random.32 dEQP-GLES31.functional.separate_shader.random.39 dEQP-GLES31.functional.separate_shader.random.64 dEQP-GLES31.functional.separate_shader.random.73 dEQP-GLES31.functional.separate_shader.random.91 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93320 Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* i965: Apply add_const_offset_to_base for vec4 VS inputs too.Kenneth Graunke2016-01-141-5/+5
| | | | | | | | This shouldn't hurt anything, and I'm about to introduce a pass that will want it. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Make add_const_offset_to_base() work at the shader level.Kenneth Graunke2016-01-141-17/+21
| | | | | | | | This makes it a pass, hiding the parameter structs and block callbacks so it's simpler to work with. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Make an is_scalar boolean in brw_compile_vs().Kenneth Graunke2016-01-141-5/+5
| | | | | | | | Shorter than compiler->scalar_stage[MESA_SHADER_VERTEX], which can help with line-wrapping. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir/builder: Add a nir_build_ivec4() convenience helper.Kenneth Graunke2016-01-141-0/+14
| | | | | | | | nir_build_ivec4 is more readable and succinct than using nir_build_imm directly, even if you have C99. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* glsl: mark explicit uniforms as explicit in other stages tooTapani Pälli2016-01-151-1/+11
| | | | | | | | | | | | | | | | If shader declares uniform explicit location in one stage but implicit in another, explicit location should be used. Patch marks implicit uniforms as explicit if they were explicit in previous stage. This makes sure that we don't treat them implicit later when assigning locations. Fixes following CTS test: ES31-CTS.explicit_uniform_location.uniform-loc-implicit-in-some-stages3 v2: move check to cross_validate_globals (Timothy) Signed-off-by: Tapani Pälli <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* i965/gen7.5+: Disable resource streamer during GPGPU workloads.Francisco Jerez2016-01-143-1/+42
| | | | | | | | | | The RS and hardware binding tables are only supported on the 3D pipeline and can lead to corruption if left enabled during a GPGPU workload. Disable it when switching to the GPGPU (or media) pipeline and re-enable it when switching back to the 3D pipeline. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Abdiel Janulgue <[email protected]>
* i965/gen7: Emit stall and dummy primitive draw after switching to the 3D ↵Francisco Jerez2016-01-141-0/+24
| | | | | | | | | pipeline. This hardware bug can supposedly lead to a hang on IVB and VLV. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen4-5: Emit MI_FLUSH as required prior to switching pipelines.Francisco Jerez2016-01-141-0/+13
| | | | | | | | | AFAIK brw_emit_select_pipeline() is only called once during context init on Gen4-5, at which point the pipeline is likely to be already idle so it may just happen to work by luck regardless of the MI_FLUSH. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6-7: Implement stall and flushes required prior to switching pipelines.Francisco Jerez2016-01-141-0/+37
| | | | | | | | | | | | | | | | | Switching the current pipeline while it's not completely idle or the read and write caches aren't flushed can lead to corruption. Fixes misrendering of at least the following Khronos CTS test: ES31-CTS.shader_image_load_store.basic-allTargets-store-fs The stall and flushes are no longer required on Gen8+. v2: Emit PIPE_CONTROL with non-zero post-sync op before the write cache flush on SNB due to hardware bug. (Ken) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93323 Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen8+: Invalidate color calc state when switching to the GPGPU pipeline.Francisco Jerez2016-01-141-0/+20
| | | | | | | | | | | This hardware bug can cause a hang on context restore while the current pipeline is set to GPGPU (BDWGFX HSD 1909593). In addition to clearing the valid bit, mark the CC state as dirty to make sure that the CC indirect state pointer is re-emitted when we switch back to the 3D pipeline. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add state bit to trigger re-emission of color calculator state.Francisco Jerez2016-01-143-0/+4
| | | | | | | | | | | | | This will be used on Gen8+ to make sure that the color calculator state pointers are re-emitted when switching back to the 3D pipeline after some GPGPU workload due to a hardware workaround. There are other state bits already defined that could be used to achieve the same effect but they all cause a ton of unrelated state to be re-emitted (e.g. BRW_NEW_STATE_BASE_ADDRESS), so just define a new one, state bits are cheap. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nv50/ir: rebase indirect temp arrays to 0, so that we use less lmem spaceIlia Mirkin2016-01-141-14/+44
| | | | | | | | | | | | | Reduces local memory usage in a lot of Metro 2033 Redux and a few KSP shaders: total local used in shared programs : 54116 -> 30372 (-43.88%) Probably modest advantage to execution, but it's an imporant prerequisite to dropping some of the TGSI optimizations done by the state tracker. Signed-off-by: Ilia Mirkin <[email protected]>
* nv50/ir: only use FILE_LOCAL_MEMORY for temp arrays that use indirectionIlia Mirkin2016-01-141-15/+50
| | | | | | | | | | | | | | | | | | | Previously we were treating any indirect temp array usage to mean that everything should end up in lmem. The MemoryOpt pass would clean a lot of that up later, but in the meanwhile we would lose a lot of opportunity for optimization. This helps a lot of Metro 2033 Redux and a handful of KSP shaders: total instructions in shared programs : 6288373 -> 6261517 (-0.43%) total gprs used in shared programs : 944051 -> 945131 (0.11%) total local used in shared programs : 54116 -> 54116 (0.00%) A typical case is for register usage to double and for instructions to halve. A future commit can also optimize local memory usage size to be reduced with better packing. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: be careful about propagating very large offsets into const loadIlia Mirkin2016-01-144-1/+19
| | | | | | | | | | | | | Indirect constbuf indexing works by using very large offsets. However if an indirect constbuf index load is const-propagated, it becomes a very large const offset. Take that into account when legalizing the SSA by moving the high parts of that offset into the file index. Also disallow very large (or small) indices on most other instructions. This fixes regressions in ubo_array_indexing/*-two-arrays piglit tests. Fixes: abd326e81b (nv50/ir: propagate indirect loads into instructions) Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: allow fragment shader inputs to use indirect indexingIlia Mirkin2016-01-141-1/+1
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* st/mesa: use surface format to generate mipmaps when availableIlia Mirkin2016-01-141-2/+8
| | | | | | | | This fixes the recently posted mipmap + texture views piglit test. Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.0 11.1" <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: don't miss changes to SPI_TMPRING_SIZEMarek Olšák2016-01-141-2/+7
| | | | | | | | | | I'm not sure about the consequences of this bug, but it's definitely dangerous. This applies to SI, CIK, VI. Cc: 11.0 11.1 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* svga: add DXGenMips command supportCharmaine Lee2016-01-1410-26/+144
| | | | | | | | | | | | | For those formats that support hw mipmap generation, use the DXGenMips command. Otherwise fallback to the mipmap generation utility. Tested with piglit, OpenGL apps (Heaven, Turbine, Cinebench) v2: make sure the texture surface was created with the render target bind flag set relocation flag to SVGA_RELOC_WRITE for the texture surface Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* svga: add num-generate-mipmap HUD queryCharmaine Lee2016-01-143-1/+12
| | | | | | | | The actual increment of the num-generate-mipmap counter will be done in a subsequent patch when hw generate mipmap is supported. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* gallium/st: add pipe_context::generate_mipmap()Charmaine Lee2016-01-1420-5/+89
| | | | | | | | | | | | | | | | This patch adds a new interface to support hardware mipmap generation. PIPE_CAP_GENERATE_MIPMAP is added to allow a driver to specify if this new interface is supported; if not supported, the state tracker will fallback to mipmap generation by rendering/texturing. v2: add PIPE_CAP_GENERATE_MIPMAP to the disabled section for all drivers v3: add format to the generate_mipmap interface to allow mipmap generation using a format other than the resource format v4: fix return type of trace_context_generate_mipmap() Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: declare struct pipe_screen in st_cb_bufferobjects.hBrian Paul2016-01-141-0/+1
| | | | To silence a compiler warning. Trivial.
* nir: Lower bitfield_extract.Matt Turner2016-01-146-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | The OpenGL specifications for bitfieldExtract() says: The result will be undefined if <offset> or <bits> is negative, or if the sum of <offset> and <bits> is greater than the number of bits used to store the operand. Therefore passing bits=32, offset=0 is legal and defined in GLSL. But the earlier SM5 ubfe/ibfe opcodes are specified to accept a bitfield width ranging from 0-31. As such, Intel and AMD instructions read only the low 5 bits of the width operand, making them not able to implement the GLSL-specified behavior directly. This commit adds ubfe/ibfe operations from SM5 and a lowering pass for bitfield_extract to to handle the trivial case of <bits> = 32 as bitfieldExtract: bits > 31 ? value : bfe(value, offset, bits) Fixes: ES31-CTS.shader_bitfield_operation.bitfieldExtract.uvec3_0 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595 Reviewed-by: Connor Abbott <[email protected]> Tested-by: Marta Lofstedt <[email protected]>
* nir: Handle <bits>=32 case in bitfield_insert lowering.Matt Turner2016-01-142-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The OpenGL specifications for bitfieldInsert() says: The result will be undefined if <offset> or <bits> is negative, or if the sum of <offset> and <bits> is greater than the number of bits used to store the operand. Therefore passing bits=32, offset=0 is legal and defined in GLSL. But the earlier SM5 bfi opcode is specified to accept a bitfield width ranging from 0-31. As such, Intel and AMD instructions read only the low 5 bits of the width operand, making them not able to implement the GLSL-specified behavior directly. This commit fixes the lowering of bitfield_insert to handle the trivial case of <bits> = 32 as bitfieldInsert: bits > 31 ? insert : bfi(bfm(bits, offset), insert, base) Fixes: ES31-CTS.shader_bitfield_operation.bitfieldInsert.uint_2 ES31-CTS.shader_bitfield_operation.bitfieldInsert.uvec4_3 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92595 Reviewed-by: Connor Abbott <[email protected]> Tested-by: Marta Lofstedt <[email protected]>
* st/mesa: add check for color logicop in blit_copy_pixels()Brian Paul2016-01-141-0/+1
| | | | | | | | We check that a bunch of raster operations are disabled in blit_copy_pixels(). We also need to check that color logicop is disabled. Reviewed-by: Marek Olšák <[email protected]>
* gallium/radeon: do not reallocate user memory buffersNicolai Hähnle2016-01-144-8/+43
| | | | | | | | | The whole point of AMD_pinned_memory is that applications don't have to map buffers via OpenGL - but they're still allowed to, so make sure we don't break the link between buffer object and user memory unless explicitly instructed to. Reviewed-by: Marek Olšák <[email protected]>
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