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* vl/dri3: use external texture as back buffers(v4)Nayan Deshmukh2017-01-173-18/+115
| | | | | | | | | | | | | | | | | | | | | dri3 allows us to send handle of a texture directly to X so this patch allows a state tracker to directly send its texture to X to be used as back buffer and avoids extra copying v2: use clip width/height to display a portion of the surface v3: remove redundant variables, fix wrapping, rename variables handle vaapi path v3.1: we need clip_width/height for every frame so we don't need to maintain it for each buffer instead use a global variable v4: In case of single gpu we can cache the buffers as applications use constant number of buffer and we can avoid calls to present extension for every frame Reviewed and Suggested-by: Leo Liu <[email protected]> Acked-by: Christian König <[email protected]> Tested-by: Andy Furniss <[email protected]> Signed-off-by: Nayan Deshmukh <[email protected]>
* anv: set UAV coherence required bit when neededIago Toral Quiroga2017-01-171-0/+51
| | | | | | | | | | | | | | | | The same we do in the OpenGL driver (comment copied from there). This is required to ensure that we execute the fragment shader stage when side-effects (such as image or ssbo stores) are present but there are no color writes. I found this while writing a test to check rendering to a framebuffer without attachments where the fragment shader does not produce any color outputs but writes to an image via imageStore(). Without this patch the fragment shader does not execute and the image is not written, which is not correct. Reviewed-by: Jason Ekstrand <[email protected]>
* anv: increase ANV_MAX_STATE_SIZE_LOG2 limit to 1 MBSamuel Iglesias Gonsálvez2017-01-172-2/+2
| | | | | | | | | | | | | | | Fixes crash in dEQP-VK.ubo.random.all_shared_buffer.48 due to a fragment shader code bigger than 128 kB. This patch increases the allocation size limit to 1 MB. v2: - Increase it to 1 MB (Jason) - Increase device->instruction_block_pool allocation size in anv_device.c (Jason) Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nv50/ir: optimize shl + andIlia Mirkin2017-01-161-0/+11
| | | | | | | | | | | | | | | | | Address loading can often end up as shl + shr + shl combinations. The latter two are equal shifts, which get converted into an and mask. However if the previous shl is more than the mask is trying to remove (in terms of low bits), we can just remove the and entirely. This reduces some large shaders by as many as 3% of instructions (out of 2K). total instructions in shared programs : 6495509 -> 6491076 (-0.07%) total gprs used in shared programs : 954621 -> 954623 (0.00%) local gpr inst bytes helped 0 0 1014 1014 hurt 0 2 0 0 Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0: enable FBFETCH with a special slot for color buffer 0Ilia Mirkin2017-01-1611-7/+174
| | | | | | | | | | | | We don't need to support all the color buffers for advanced blend, just cb0. For Fermi, we use the special binding slots so that we don't overlap with user textures, while Kepler+ gets a dedicated position for the fb handle in the driver constbuf. This logic is only triggered when a FBFETCH is actually present so it should be a no-op most of the time. Signed-off-by: Ilia Mirkin <[email protected]>
* st/mesa: add support for advanced blend when fb can be fetched fromIlia Mirkin2017-01-164-8/+37
| | | | | | | | | This implements support for emitting FBFETCH ops, using the existing lowering pass for advanced blend logic, and disabling hw blend when advanced blending is enabled. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add flags parameter to texture barrierIlia Mirkin2017-01-1614-16/+24
| | | | | | | | This is so that we can differentiate between flushing any framebuffer reading caches from regular sampler caches. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add PIPE_CAP_TGSI_FS_FBFETCHIlia Mirkin2017-01-1617-2/+20
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium: add FBFETCH opcode to retrieve the current sample valueIlia Mirkin2017-01-163-2/+15
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* mesa: allow BlendBarrier to be used without support for full fb fetchIlia Mirkin2017-01-161-1/+2
| | | | | | | | The extension spec is not currently published, so it's a bit premature to require it for BlendBarrier usage. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* glsl: avoid treating fb fetches as output reads to be loweredIlia Mirkin2017-01-161-1/+1
| | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
* radv/meta: split color renderpass creation out.Dave Airlie2017-01-171-38/+49
| | | | | | | | This is just prep work for layered clears, it doesn't change anything. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv: Support multiple devices.Bas Nieuwenhuizen2017-01-162-44/+19
| | | | | | | | | | | | | | Pretty straightforward. Also deleted the big comment block as it is a pretty standard pattern for filling in arrays. Also removed the error message on non-existent devices, as getting 7 errors printed to the console each time you enumerate the devices is pretty confusing. v2: Add constant for number of DRM devices. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* radv: Get physical device from radv_device instead of the instance.Bas Nieuwenhuizen2017-01-169-49/+50
| | | | | Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
* nvc0: true up exposing of the HW_METRIC_QUERY_GROUP for maxwellIlia Mirkin2017-01-161-2/+2
| | | | | | | This had been updated in one place but not the other. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* radv/ac: use ctx->voidt in more places. (v2)Dave Airlie2017-01-171-11/+11
| | | | | | | | | Just noticed this while in the area. v2: one replacement was incorrect. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radv/meta: consolidate the depth stencil clear renderpassesDave Airlie2017-01-172-41/+48
| | | | | | | | We only need one per samples (maybe not even that), reduce all the unneeded ones. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* nv50/ir: handle new DDIV op which will be used for double divisionsIlia Mirkin2017-01-161-0/+3
| | | | | | | The existing lowering is in place to lower that to RCP + MUL, or fancier things down the line if necessary. Signed-off-by: Ilia Mirkin <[email protected]>
* tgsi: add DDIV instructionNicolai Hähnle2017-01-164-1/+17
| | | | | | | | | Double-precision division, to allow more precision than a DRCP + DMUL sequence. Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix R600_DEBUG=nooptvariantNicolai Hähnle2017-01-161-1/+1
| | | | | Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Vedran Miletić <[email protected]>
* i965: Make BLORP disable the NP Z PMA stall fix.Kenneth Graunke2017-01-161-0/+4
| | | | | | | | This may fix GPU hangs on Gen8. I don't know if it does though. Cc: [email protected] Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Enable OpenGL 4.5 on Haswell.Kenneth Graunke2017-01-162-2/+2
| | | | | | | | Everything is in place and the test results look solid. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* radeonsi: implement GL_FIXED vertex formatMarek Olšák2017-01-163-7/+20
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: implement 32-bit SNORM/UNORM/SSCALED/USCALED vertex formatsMarek Olšák2017-01-163-18/+90
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: make fix_fetch 64-bitMarek Olšák2017-01-166-9/+18
| | | | | | v2: add u_bit_consecutive64 Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/hud: avoid buffer overrunThomas Hindoe Paaboel Andersen2017-01-161-2/+4
| | | | | | | | | | | | Renaming data sources was added in e8bb97ce30051b999a4a69c9b27884daeb8d71e6 It was possible to use a new name longer than the name array in hud_graph of 128. This patch truncates the name to fit the array. CC: Marek Olšák <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* gallium/radeon: add GPU-shaders-busy HUD queryMarek Olšák2017-01-164-1/+31
| | | | | | | It should be close to the GPU load, but it can be much lower if something is stalling shader execution (e.g. CP DMA). Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/radeon: make the GPU load / GRBM_STATUS monitoring extensibleMarek Olšák2017-01-163-32/+53
| | | | | | The next patch will add SPI_BUSY monitoring. Reviewed-by: Nicolai Hähnle <[email protected]>
* radeonsi: show average results per frame for perf counters in HUDMarek Olšák2017-01-161-1/+1
| | | | | | so that the graphs are independent from FPS. Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/hud: disable queries during HUD draw callsMarek Olšák2017-01-163-1/+29
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* gallium/hud: increase the vertex buffer size for background quadsMarek Olšák2017-01-161-1/+1
| | | | Reviewed-by: Nicolai Hähnle <[email protected]>
* st/va: delay calling begin_frame until we have all parametersNayan Deshmukh2017-01-161-3/+3
| | | | | | | | | | If begin_frame is called before setting intra_matrix and non_intra_matrix it leads to segmentation faults when vl_mpeg12_decoder.c is used. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92634 Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]>
* i965: Use align1 mode for barrier messages.Kenneth Graunke2017-01-151-0/+3
| | | | | | | | | | | | | | In commit 7428e6f86ab5 we switched the barrier SEND message's destination type to UW to avoid problems in SIMD16 compute shaders. Tessellation control shaders also use barriers, and in vec4 mode, we were emitting them in align16 mode. The simulator warns that only UD, D, F, and DF are valid destination types - UW is technically illegal. So, switch to align1 mode. Either mode should work fine. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nvc0/ir: emit FMZ flag when requested on FFMAIlia Mirkin2017-01-151-0/+4
| | | | Signed-off-by: Ilia Mirkin <[email protected]>
* nir/gcm: fix a bug with metadata handlingConnor Abbott2017-01-141-3/+3
| | | | | | | | | | | We were using impl->num_blocks, but that isn't guaranteed to be up-to-date until after the block_index metadata is required. If we were unlucky, this could lead to overwriting memory. Noticed by inspection. Signed-off-by: Connor Abbott <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radv: generate entrypoints from vk.xmlLionel Landwerlin2017-01-142-60/+56
| | | | | | | | | | v2: rework entry point iteration (Jason) cleanup unused imports v3: don't drop header installation (Emil) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* anv: generate entry points from vk.xmlLionel Landwerlin2017-01-142-65/+71
| | | | | | | | | | | v2: rework entry point iteration (Jason) cleanup unused imports v3: don't drop header installation (Emil) Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* vulkan: add API registryLionel Landwerlin2017-01-142-1/+4906
| | | | | Signed-off: Lionel Landwerlin <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* include: update Vulkan headersLionel Landwerlin2017-01-142-5/+244
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Acked-by: Jason Ekstrand <[email protected]>
* radv: make device extension setup dynamicAndres Rodriguez2017-01-142-65/+130
| | | | | | | | | | | | | | Each physical device may have different extensions than one another. Furthermore, depending on the software stack, some extensions may not be accessible. If an extension is conditional, it can be registered only when necessary. v2: removed unused function and fixed indentation Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename global extension properties structsAndres Rodriguez2017-01-141-14/+14
| | | | | | | | | | | | All extension arrays are global, but only one of them refers to instance extensions. The device extension array refers to extensions that are common across all physical devices. This disctinction will be more imporant once we have dynamic extension support for devices. Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use a winsys context per-queue, instead of per device v2Andres Rodriguez2017-01-143-21/+22
| | | | | | | | | | | | | | | Queues are independent execution streams. The vulkan spec provides no ordering guarantees for different queues. By using a single context for all queues, we are forcing all commands into an unecessary FIFO ordering. This change is a preparation step to allow our-of-ordering scheduling of certain work tasks. v2: Fix a rebase error with radv_QueueSubmit() and trace_bo Signed-off-by: Andres Rodriguez <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* nir: optimise min/max fadd combosTimothy Arceri2017-01-142-0/+26
| | | | | | | | | | | | | | | | shader-db results BDW: total instructions in shared programs: 13060410 -> 13060313 (-0.00%) instructions in affected programs: 24533 -> 24436 (-0.40%) helped: 88 HURT: 0 total cycles in shared programs: 256585692 -> 256586698 (0.00%) cycles in affected programs: 647290 -> 648296 (0.16%) helped: 35 HURT: 30 Reviewed-by: Matt Turner <[email protected]>
* i965: Move Gen4-5 interpolation stuff to brw_wm_prog_data.Kenneth Graunke2017-01-1311-70/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | This fixes glxgears rendering, which had surprisingly been broken since late October! Specifically, commit 91d61fbf7cb61a44adcaae51ee08ad0dd6b. glxgears uses glShadeModel(GL_FLAT) when drawing the main portion of the gears, then uses glShadeModel(GL_SMOOTH) for drawing the Gouraud-shaded inner portion of the gears. This results in the same fragment program having two different state-dependent interpolation maps: one where gl_Color is flat, and another where it's smooth. The problem is that there's only one gen4_fragment_program, so it can't store both. Each FS compile would trash the last one. But, the FS compiles are cached, so the first one would store FLAT, and the second would see a matching program in the cache and never bother to compile one with SMOOTH. (Clearing the program cache on every draw made it render correctly.) Instead, move it to brw_wm_prog_data, where we can keep a copy for every specialization of the program. The only downside is bloating the structure a bit, but we can tighten that up a bit if we need to. This also lets us kill gen4_fragment_program entirely! Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* anv: remove some unused macros and functionsGrazvydas Ignotas2017-01-132-34/+0
| | | | | | VK_ICD_WSI_PLATFORM_MAX is used, but a duplicate from wsi_common.h . Acked-by: Jason Ekstrand <[email protected]>
* anv: Default PointSize to 1.0 if not written by the shaderJason Ekstrand2017-01-131-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Vulkan rules for point size are a bit whacky. If you only have a vertex shader and you use points, then you must write PointSize in your vertex shader. If you have a geometry or tessellation shader, then it's dependent on the shaderTessellationAndGeometryPointSize device feature. From the Vulkan 1.0.38 specification: "shaderTessellationAndGeometryPointSize indicates whether the PointSize built-in decoration is available in the tessellation control, tessellation evaluation, and geometry shader stages. If this feature is not enabled, members decorated with the PointSize built-in decoration must not be read from or written to and all points written from a tessellation or geometry shader will have a size of 1.0. This also indicates whether shader modules can declare the TessellationPointSize capability for tessellation control and evaluation shaders, or if the shader modules can declare the GeometryPointSize capability for geometry shaders. An implementation supporting this feature must also support one or both of the tessellationShader or geometryShader features." In other words, if the feature is disbled (the client can disable features!) then they don't write PointSize and we provide a 1.0 default but if the feature is enabled, they do write PointSize and we use the one they wrote in the shader. There are at least two valid ways we can implement this: 1) Track whether or not shaderTessellationAndGeometryPointSize is enabled and set the 3DSTATE_SF bits based on that and what stages are enabled, ignoring the shader source. 2) Just look at the last geometry stage VUE map and see if they wrote PointSize and set the 3DSTATE_SF accordingly. The second solution is the easiest and the most robust against invalid usage of the Vulkan API, so we choose to go with that one. This fixes all of the dEQP-VK.tessellation.primitive_discard.*point_mode tests. The tests are also broken because they unconditionally enable shaderTessellationAndGeometryPointSize if it's supported by the implementation and then don't write PointSize in the evaluation shader. However, since this is the "robust against invalid API usage" solution, the tests happily pass. :-) Reviewed-by: Kenneth Graunke <[email protected]>
* anv/pipeline: Replace get_fs_input_map with get_last_vue_prog_dataJason Ekstrand2017-01-133-22/+10
| | | | | | This lets us delete a helper from genX_pipeline.c Reviewed-by: Lionel Landwerlin <[email protected]>
* i965/vec4: Fix mapping attributesJuan A. Suarez Romero2017-01-132-23/+11
| | | | | | | | | | | | | | | | | | This patch reverts 57bab6708f2bbc1ab8a3d202e9a467963596d462, which was causing issues with ILK and earlier VS programs. 1. brw_nir.c: Revert "i965/vec4/nir: vec4 also needs to remap vs attributes" Do not perform a remap in vec4 backend. Rather, do it later when setup attributes 2. brw_vec4.cpp: This fixes mapping ATTRx to proper GRFn. Suggested-by: Kenneth Graunke <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99391 [[email protected]: merge Juan's two patches from bugzilla] Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* anv: Move nir_lower_wpos_center after dead variable elimination.Kenneth Graunke2017-01-131-3/+3
| | | | | | | | | | | | | | | | When multiple shader stages exist in the same SPIR-V module, we compile all entry points and their inputs/outputs, then dead code eliminate the ones not related to the specific entry point later. nir_lower_wpos_center was being run prior to eliminating those random other variables, which made it trip up, thinking it found gl_FragCoord when it actually found something else like gl_PerVertex[3]. Fixes dEQP-VK.spirv_assembly.instruction.graphics.module.same_module. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix textureGather with RG32I/UI on Gen7.Kenneth Graunke2017-01-132-8/+37
| | | | | | | | | | | | | | | | | | | According to the "Gather4 R32G32_FLOAT Bug" internal documentation page, the R32G32_UINT and R32G32_SINT formats are affected by the same bug as R32G32_FLOAT. Applying the same workarounds should be viable - apparently the R32G32_FLOAT_LD format shouldn't corrupt integer data which is NaN or other sketchy floating point values. One irritating caveat is that, because it's a FLOAT format, the alpha channel or any set to SCS_ONE return 0x3f8 (1.0) rather than integer 1. So we need shader code to whack those channels to 1. Fixes GL45-CTS.texture_gather.plain-gather-int-cube-rg on Haswell. v2: Fix swizzle component zeroing (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
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