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* radeonsi: reduce overhead for resident textures which need depth decompressionSamuel Pitoiset2017-06-184-8/+29
* radeonsi: use util_dynarray_foreach for bindless resourcesSamuel Pitoiset2017-06-182-129/+46
* mesa/util: add util_dynarray_clear() helperSamuel Pitoiset2017-06-181-0/+6
* gallium/radeon: add a new HUD query for the number of resident handlesSamuel Pitoiset2017-06-184-0/+12
* i965/gen4: Refactor depth/stencil rebaseTopi Pohjolainen2017-06-181-180/+63
* i965: Drop depth/stencil miptree pointers in alignment workaroundTopi Pohjolainen2017-06-182-15/+3
* i965/gen4: Simplify depth/stencil invalidate checkTopi Pohjolainen2017-06-181-13/+3
* i965/gen4: Remove redundant check for depth when rebasing stencilTopi Pohjolainen2017-06-181-51/+12
* i965/gen4: Remove non-existing stencil and hiz buffer setupTopi Pohjolainen2017-06-182-117/+14
* android: ac: add missing libdrm_amdgpu shared dependencyMauro Rossi2017-06-171-0/+3
* r600: include libelf headers only as neededEmil Velikov2017-06-171-0/+2
* radeonsi: include ac_binary.h for struct ac_shader_binaryEmil Velikov2017-06-171-2/+2
* r600, radeon: move radeon_shader_binary_{init,clean} back to radeonEmil Velikov2017-06-173-23/+28
* ac: resolve conflicts introduced with "ac: remove amdgpu.h dependency"Emil Velikov2017-06-171-1/+3
* i965/gen4: Set depth offset when there is stencil attachment onlyTopi Pohjolainen2017-06-171-0/+6
* i965/gen6: Remove dead code in hiz surface setupTopi Pohjolainen2017-06-171-7/+6
* intel/isl/gen6: Allow arrayed stencilTopi Pohjolainen2017-06-171-1/+0
* svga: add new num-failed-allocations HUD queryBrian Paul2017-06-165-2/+26
* gallium/hud: support GALLIUM_HUD_DUMP_DIR feature on WindowsBrian Paul2017-06-161-6/+30
* svga: add a few minor commentsBrian Paul2017-06-162-1/+6
* mesa: whitespace fixes in enable.cBrian Paul2017-06-161-68/+68
* i965: Convert SF_STATE to genxml.Rafael Antognolli2017-06-165-288/+83
* genxml: The viewport state offset is actually an address.Rafael Antognolli2017-06-161-1/+1
* genxml: Rename fields to match gen6+.Rafael Antognolli2017-06-163-3/+3
* genxml: Rename SF_STATE field to match gen6+.Rafael Antognolli2017-06-163-9/+9
* i965: aa_line_distance_mode should be before the padding.Rafael Antognolli2017-06-161-1/+1
* swr/rast: Fix read-back of viewport array indexTim Rowley2017-06-1610-117/+182
* swr/rast: Refactor includes to limit simdintrin.h usageTim Rowley2017-06-1616-1079/+1147
* swr/rast: Fix read-back of render target array indexTim Rowley2017-06-165-13/+18
* swr/rast: Adjust cast for gcc warningTim Rowley2017-06-161-1/+1
* swr/rast: Don't transition hottile resolved->dirty during store tilesTim Rowley2017-06-161-1/+4
* swr/rast: gen_llvm_types.py support for SIMD256/SIMD512Tim Rowley2017-06-161-6/+6
* swr/rast: Properly size GS stage scratch spaceTim Rowley2017-06-161-1/+1
* swr/rast: Fix early z / query interactionTim Rowley2017-06-161-0/+4
* swr/rast: Share vertex memory between VS input/outputTim Rowley2017-06-161-5/+2
* swr/rast: Add support for dynamic vertex size for VS outputTim Rowley2017-06-163-15/+23
* swr/rast: SIMD16 FE - improve calcDeterminantIntVerticalTim Rowley2017-06-161-12/+20
* swr/rast: Add support to PA for variable sized verticesTim Rowley2017-06-164-26/+38
* swr/rast: Rework attribute layoutTim Rowley2017-06-164-66/+103
* swr/rast: Remove explicit primitive id slot in the vertex layoutTim Rowley2017-06-167-58/+33
* swr/rast: Fix invalid 16-bit format traits for A1R5G5B5Tim Rowley2017-06-161-100/+48
* swr/rast: Implement JIT shader caching to diskTim Rowley2017-06-1610-18/+358
* gallium/docs: improve docs for SAMPLE_POS, SAMPLE_INFO, TXQS, MSAA semanticsBrian Paul2017-06-161-11/+47
* svga: add some missing SVGA_STATS_* enum values, prefix stringsBrian Paul2017-06-161-2/+15
* radeonsi: add new polaris12 pci idAlex Deucher2017-06-161-0/+1
* swr: Don't crash when encountering a VBO with stride = 0.Bruce Cherniak2017-06-161-7/+18
* intel/isl: Add the maximum surface size limitAnuj Phogat2017-06-161-0/+22
* intel/isl: Use uint64_t to store total surface sizeAnuj Phogat2017-06-162-2/+3
* i965: Mark freshly allocate bo as idleChris Wilson2017-06-161-0/+1
* etnaviv: add rs-operations sw queryChristian Gmeiner2017-06-165-0/+8
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