summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* freedreno/ir3: support load_front_face intrinsicRob Clark2016-01-301-2/+14
* freedreno: limit string marker to max packet sizeRob Clark2016-01-301-0/+3
* nvc0: avoid crashing when there are holes in vertex array bindingsIlia Mirkin2016-01-291-3/+13
* nvc0: enable atomic counters and ssboIlia Mirkin2016-01-294-4/+10
* nv50/ir: handle new TGSI MEMBAR opcodeIlia Mirkin2016-01-291-0/+8
* nvc0/ir: fix atomic compare-and-swap argumentsIlia Mirkin2016-01-293-5/+8
* nv50/ir: add support for indirect buffer loadingIlia Mirkin2016-01-292-10/+31
* nv50/ir: add SUQ op by reading the info from driver constbufIlia Mirkin2016-01-296-3/+21
* nv50/ir: add support for BUFFER accessesIlia Mirkin2016-01-296-11/+147
* nvc0: handle shader buffer memory barrierIlia Mirkin2016-01-291-0/+4
* nvc0: add state management for shader buffersIlia Mirkin2016-01-295-8/+111
* nvc0: double per-shader stage driver constants areaIlia Mirkin2016-01-293-15/+15
* trace: add support for set_shader_buffersIlia Mirkin2016-01-293-0/+60
* st/mesa: enable ARB_shader_storage_buffer_object when supportedIlia Mirkin2016-01-291-0/+1
* st/mesa: add shader buffer barrier bitIlia Mirkin2016-01-292-0/+5
* st/mesa: add support for memory barrier intrinsicsIlia Mirkin2016-01-291-0/+45
* st/mesa: use RESQ to find buffer sizeIlia Mirkin2016-01-291-4/+18
* st/mesa: add support for SSBO binding and GLSL intrinsicsIlia Mirkin2016-01-299-8/+397
* st/mesa: add atomic counter supportIlia Mirkin2016-01-2910-8/+330
* mesa: add PROGRAM_IMMEDIATE, PROGRAM_BUFFERIlia Mirkin2016-01-292-1/+2
* glsl: keep track of ssbo variable being accessed, add access paramsIlia Mirkin2016-01-295-6/+57
* glsl: always initialize image_* fields, copy them on interface initIlia Mirkin2016-01-293-1/+12
* tgsi: add MEMBAR opcode to handle memoryBarrier* GLSL intrinsicsIlia Mirkin2016-01-293-2/+24
* winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*Michel Dänzer2016-01-291-10/+9
* winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESSMichel Dänzer2016-01-291-0/+2
* nv50/ir: optimize mad/fma with third argument 0 to mulKarol Herbst2016-01-281-0/+21
* nv50/ir: run DCE backwardsKarol Herbst2016-01-281-3/+3
* nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))Karol Herbst2016-01-281-0/+8
* glsl: disallow implicit conversions in ESSL shadersIlia Mirkin2016-01-282-0/+11
* radeonsi: Add option for SI schedulerAxel Davy2016-01-283-1/+7
* glsl: double-precision values don't support interpolationSamuel Iglesias Gonsálvez2016-01-281-2/+7
* vc4: Throttle outstanding rendering after submission.Eric Anholt2016-01-271-0/+9
* vc4: Don't record the seqno of a failed job submit.Eric Anholt2016-01-271-2/+2
* i965/skl: Utilize new 5th bit for gateway messagesBen Widawsky2016-01-271-2/+4
* glsl: only expose double mod when doubles are availableIlia Mirkin2016-01-271-17/+18
* nv50/ir: fix memory corruption when spilling and redoing RAKarol Herbst2016-01-261-0/+3
* glsl: remove old FINISHMETimothy Arceri2016-01-271-2/+0
* configure.ac: don't require EGL/DRM and GBM if OpenGL is disabledMarek Olšák2016-01-261-0/+5
* r600,compute: Plug few memory leaksJan Vesely2016-01-268-21/+55
* r600: Typos and whitespace fixesJan Vesely2016-01-263-7/+7
* radeonsi: fix clover crashMarek Olšák2016-01-261-1/+1
* radeonsi: fix shader precompilation for shader-dbMarek Olšák2016-01-261-9/+35
* glsl: add GL_OES_geometry_point_size and conditionalize gl_PointSizeIlia Mirkin2016-01-265-1/+17
* glsl: move to compiler/Emil Velikov2016-01-26497-84/+498
* nir: move to compiler/Emil Velikov2016-01-26105-157/+310
* compiler: move the glsl_types C wrapper alongside their C++ brethrenEmil Velikov2016-01-266-7/+8
* nir: move glsl_types.{cpp,h} to compilerEmil Velikov2016-01-2670-76/+68
* nir: move shader_enums.[ch] to compilerEmil Velikov2016-01-2624-15/+116
* compiler: introduce a libcompiler static libraryEmil Velikov2016-01-269-5/+35
* gallium/ddebug: add 'verbose' optionNicolai Hähnle2016-01-265-5/+12
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 22:27:06 +0000