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* gallium/radeon: clean left-shift undefined behaviorNicolai Hähnle2016-05-0711-3989/+3989
| | | | | | | | | | | | | | Shifting into the sign bit of a signed int is undefined behavior. Unfortunately, there are potentially many places where this happens using the register macros. This commit is the result of running sed -ie "s/(((\(\w\+\)) & 0x\(\w\+\)) << \(\w\+\))/(((unsigned)(\1) \& 0x\2) << \3)/g" on all header files in gallium/{r600,radeon,radeonsi}. Reviewed-by: Marek Olšák <[email protected]>
* gallium: fix various undefined left shifts into sign bitNicolai Hähnle2016-05-076-8/+8
| | | | | | | | | Funnily enough, some of these were turned into a compile-time error by gcc with -fsanitize=undefined ("initializer is not a constant"). Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* compiler/glsl: do not downcast list sentinelNicolai Hähnle2016-05-071-1/+4
| | | | | | This crashes gcc's undefined behaviour sanitizer. Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: fix another undefined left shiftNicolai Hähnle2016-05-071-1/+1
| | | | | | Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* mesa/main: define _NEW_xxx flags as unsigned shiftsNicolai Hähnle2016-05-071-30/+30
| | | | | | | | | Since 1 << 31 complains about undefined behaviour; the others are changed only for consistency. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: Compute correct LDS size for fragment shaders.Bas Nieuwenhuizen2016-05-061-3/+6
| | | | | | | | No sure where the 36 came from, but we clearly need at least 48 bytes per attribute per primitive. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* vc4: Add support for loading immediate values in QIR.Eric Anholt2016-05-064-0/+32
| | | | | | | This will be used for resetting the uniform stream in the presence of branching, but may also be useful as an optimization to reduce how many uniforms we have to copy out per draw call (in exchange for increasing icache pressure).
* vc4: Make vc4_qpu_validate() produce more verbose failures.Eric Anholt2016-05-061-35/+71
| | | | | | Seeing the expansion of a QPU_GET_FIELD in an assert isn't very informative, and it's hard find what's going wrong without getting a dump of the instruction that failed.
* vc4: Add a small QIR validate pass.Eric Anholt2016-05-064-0/+127
| | | | | This has caught a couple of bugs during loop development so far, and I should probably have written it long ago.
* vc4: Fix the src count on exp2/log2.Eric Anholt2016-05-061-2/+2
| | | | Found by the upcoming QIR validate pass.
* vc4: Reuse QPU disasm's cond flags in QIR.Eric Anholt2016-05-063-27/+46
| | | | In the process, this made me flatten out the "%s%s%s%s" fprintf arguments.
* vc4: When emitting an instruction to an existing temp, mark it non-SSA.Eric Anholt2016-05-061-0/+2
| | | | Prevents a bug in the later control-flow support series.
* vc4: Make sure that we don't overwrite the signal for PROG_END.Eric Anholt2016-05-061-0/+8
| | | | | | | | We should have already emitted a NOP due to the last instruction being a TLB or VPM write. However, if you disable dead code elimination then you might get dead code at the end, and that dead code might have the signal bits set to something non-default, at which point you die in assertion failure.
* nvc0: unreference images when the context is destroyedSamuel Pitoiset2016-05-061-0/+4
| | | | | | | Like other resources, we need to unreference all images. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* nir: Remove spurious return from void function.Jose Fonseca2016-05-061-2/+0
| | | | | | | | Left over from 450c0613627d5a472fcf1122c15b66988abfb372. Trivial. Built locally with clang and gcc. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95296
* radeonsi: set DECOMPRESS_Z_ON_FLUSH if nr_samples >= 4Marek Olšák2016-05-061-1/+2
| | | | | | | | Vulkan always sets this. It only affects in-place Z decompression. This is recommended for performance, but what app uses MSAA depth texturing? Reviewed-by: Nicolai Hähnle <[email protected]>
* r600g: use the hw MSAA resolving if formats are compatibleMarek Olšák2016-05-061-1/+2
| | | | | | | This allows resolving RGBA into RGBX. This should improve HL2 Lost Coast performance. Reviewed-by: Alex Deucher <[email protected]>
* Revert "i965: Switch to scalar TCS by default."Kenneth Graunke2016-05-051-1/+1
| | | | | | | This reverts commit b593737ed8349b280fa29242c35f565b59ab3025. Apparently it causes GPU hangs on some image load store tests. Let's turn it back off until we figure out why.
* st/omx/enc: fix incorrect reference picture order for B framesLeo Liu2016-05-051-7/+12
| | | | | | | | | Stacking frames is for driver that's capable to do dual instances encoding. Such feature is not enabled for B frames currently. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: "11.1 11.2" <[email protected]>
* i965/fs: Move handling of samples_identical into the switch statementJason Ekstrand2016-05-051-21/+19
| | | | | This is where we handle texop_texture_samples so it makes things more consistent.
* i965/fs: Simplify texture destination fixupsJason Ekstrand2016-05-051-21/+11
| | | | | | | | | | | | | | | | | | | | | | There are a few different fixups that we have to do for texture destinations that re-arrange channels, fix hardware vs. API mismatches, or just shrink the result to fit in the NIR destination. These were all being done in a somewhat haphazard manner. This commit replaces all of the shuffling with a single LOAD_PAYLOAD operation at the end and makes it much easier to insert fixups between the texture instruction itself and the LOAD_PAYLOAD. Shader-db results on Haswell: total instructions in shared programs: 6227035 -> 6226669 (-0.01%) instructions in affected programs: 19119 -> 18753 (-1.91%) helped: 85 HURT: 0 total cycles in shared programs: 56491626 -> 56476126 (-0.03%) cycles in affected programs: 672420 -> 656920 (-2.31%) helped: 92 HURT: 42
* i965/fs: stop inclinding glsl/ir.h in brw_fs.hJason Ekstrand2016-05-052-1/+1
| | | | We are no longer using anything from GLSL IR in the FS backend.
* i965/fs: Merge nir_emit_texture and emit_textureJason Ekstrand2016-05-053-238/+162
| | | | | | | The fs_visitor::emit_texture helper originated when we still had both NIR and IR visitors for the FS backend. Since the old visitor was removed, emit_texture serves no real purpose beyond arbitrarily splitting heavily-linked code across two functions.
* nir: remove now-unused nir_foreach_block*_call()Connor Abbott2016-05-051-38/+0
| | | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* vc4: fixup for new nir_foreach_block()Connor Abbott2016-05-054-48/+20
| | | | Reviewed-by: Eric Anholt <[email protected]>
* ir3: fixup for new nir_foreach_block()Connor Abbott2016-05-051-30/+21
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* nir/lower_double_ops: fixup for new nir_foreach_block()Jason Ekstrand2016-05-051-23/+9
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir/lower_double_pack: fixup for new nir_foreach_block()Jason Ekstrand2016-05-051-26/+21
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir/gather_info: fixup for new foreach_block()Jason Ekstrand2016-05-051-5/+5
| | | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Connor Abbott <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir/lower_two_sided_color: fixup for new foreach_block()Connor Abbott2016-05-051-3/+5
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir/lower_tex: fixup for new foreach_block()Connor Abbott2016-05-051-25/+22
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir/lower_outputs_to_temporaries: fixup for new foreach_block()Connor Abbott2016-05-051-16/+12
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Switch to scalar TCS by default.Kenneth Graunke2016-05-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Normally, we expect SIMD8 shaders to be more instructions than SIMD4x2 shaders, as it takes four instructions to operate on a vec4, rather than a single instruction. However, the benefit is that it can process 8 objects per shader thread instead of 2. Surprisingly, the shader-db statistics show an improvement in both instruction and cycle counts: Synmark: -31.25% instructions, -29.27% cycles, 0 hurt. Tessmark: -36.92% instructions, -37.81% cycles, 0 hurt. Unigine Heaven: -3.42% instructions, -17.95% cycles, 0 hurt. Shadow of Mordor: +13.24% instructions (26 with fewer instructions, 45 with more), -5.23% cycles (44 with fewer cycles, 27 with more cycles). Presumably, this is because the SIMD8 URB messages are a much more natural fit than the SIMD4x2 URB messages - there's a ton less header setup. I benchmarked Shadow of Mordor and Unigine Heaven on my Skylake GT3e, and the performance seems to be the same or increase ever so slightly (< 1 FPS difference). So I believe it's strictly superior. There's also a lot more optimization potential we can do in scalar mode. This will also help us finish fp64 support, as scalar support is going to land much sooner than vec4-mode support. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Optimize out stores of undefs.Kenneth Graunke2016-05-051-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of cycle count changes in shader-db, but it's basically a wash. However, with the Broadwell scalar TCS backend enabled, many Shadow of Mordor shaders benefit from this patch. Because we don't batch up output writes for TCS, vec4 outputs might not have all components defined. Many output writes have a value of undef, which is useless. With scalar TCS, stats for tessellation shaders on Broadwell: total instructions in shared programs: 1283000 -> 1280444 (-0.20%) instructions in affected programs: 34302 -> 31746 (-7.45%) helped: 71 HURT: 0 total cycles in shared programs: 10798768 -> 10780682 (-0.17%) cycles in affected programs: 158004 -> 139918 (-11.45%) helped: 71 HURT: 0 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Replace vecN(undef, undef, ...) with a single undef.Kenneth Graunke2016-05-051-0/+33
| | | | | | | | | | | | | | | | | | | | | | | shader-db statistics on Broadwell: total instructions in shared programs: 8963409 -> 8962455 (-0.01%) instructions in affected programs: 60858 -> 59904 (-1.57%) helped: 318 HURT: 0 total cycles in shared programs: 71408022 -> 71406276 (-0.00%) cycles in affected programs: 398416 -> 396670 (-0.44%) helped: 199 HURT: 51 GAINED: 1 The only shaders affected were in Dota 2 Reborn. It also sets up for the next optimization. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* nir: Rename opt_undef_alu to opt_undef_csel; update comments.Kenneth Graunke2016-05-051-12/+13
| | | | | | | | | | | | This better reflects what it does. I plan to add other ALU optimizations as well, so the old name would be confusing. In preparation for that, also move the file comments about csels above the opt_undef_csel function, and delete the ones about there not being other optimizations. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Rework passthrough TCS checks.Kenneth Graunke2016-05-054-2/+5
| | | | | | | | | | According to Timothy, using program_string_id == 0 to identify the passthrough TCS is going to be problematic for his shader cache work. So, change it to strcmp() the name at visitor creation time. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* swr: [rasterizer core] Faster modulo operator in ProcessVertsTim Rowley2016-05-051-1/+4
| | | | | | Avoid % operator, since we know that curVertex is always incrementing. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer] Small warning cleanupTim Rowley2016-05-052-8/+4
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer] Add SWR_ASSUME / SWR_ASSUME_ASSERT macrosTim Rowley2016-05-052-14/+52
| | | | | | Fix static code analysis errors found by coverity on Linux Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer] Miscellaneous backend changesTim Rowley2016-05-053-22/+31
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer] Add support for X24_TYPELESS_G8_UINT formatTim Rowley2016-05-053-7/+41
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Fix printing bugs for tracing.Tim Rowley2016-05-051-81/+24
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer memory] Add missing store tiles functionTim Rowley2016-05-051-1/+4
| | | | | | Storing color hot tile to 8bit w-major stencil format. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer jitter] Add asserts for supported formats in fetch shaderTim Rowley2016-05-051-0/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Fix thread allocationTim Rowley2016-05-051-17/+47
| | | | | | | | Fix windows in 32-bit mode when hyperthreading is disabled on Xeons. Some support for asymmetric processor topologies. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer core] Fix threadviz support in bucketsTim Rowley2016-05-053-12/+14
| | | | | | | Need to do lazy eval of the threadviz knob since order of globals is undefined. Reviewed-by: Bruce Cherniak <[email protected]>
* swr: [rasterizer] Whitespace cleanup and misc changesTim Rowley2016-05-055-5/+2
| | | | Reviewed-by: Bruce Cherniak <[email protected]>
* radeonsi: mark descriptor loads as using dynamically uniform indicesNicolai Hähnle2016-05-051-5/+17
| | | | | | | | This tells LLVM to always use SMEM loads for descriptors. It fixes a regression in piglit's arb_shader_storage_buffer_object/execution/indirect.shader_test that was caused by LLVM r268259 (but the proper fix is really here in Mesa). Reviewed-by: Marek Olšák <[email protected]>
* i965/fs: Don't follow pow with an instruction with two dest regs.Matt Turner2016-05-051-0/+18
| | | | | | | | | | | | | | | | | Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on Gen >= 8 platforms. Evidently that commit allowed the scheduler to make different choices that somehow finally ran afoul of a hardware bug in which POW and FDIV instructions may not be followed by an instruction with two destination registers (including compressed instructions). I presume the conditions are more complex than that, but the internal hardware bug report (BDWGFX bug_de 1696294) does not contain much more information. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94924 Reviewed-by: Topi Pohjolainen <[email protected]> [v1] Tested-by: Mark Janes <[email protected]> [v1] Reviewed-by: Francisco Jerez <[email protected]>
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