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* i965: No longer reemit textures on BRW_NEW_UNIFORM_BUFFERChris Forbes2014-10-161-2/+1
* i965: Dirty state in BO reallocation based on usage historyChris Forbes2014-10-161-1/+4
* i965: Have mesa flag BRW_NEW_TEXTURE_BUFFER when a TexBO binding changesChris Forbes2014-10-161-0/+1
* i965: Add new dirty flag for new TexBOs.Chris Forbes2014-10-163-0/+4
* mesa: Mark buffer objects that are used as TexBOsChris Forbes2014-10-162-0/+9
* mesa: Mark buffer objects which are bound as UBOsChris Forbes2014-10-161-0/+6
* mesa: Add usage history bitfield to buffer objectsChris Forbes2014-10-161-0/+9
* vc4: correctly include the source filesEmil Velikov2014-10-162-3/+1
* i965/fs: don't make a fake ir_texture in the Mesa IR frontendConnor Abbott2014-10-151-14/+5
* i965/fs: Refactor the texture emission logic into a single function.Kenneth Graunke2014-10-153-104/+144
* i965/fs: Make gather_channel() not use ir_texture.Connor Abbott2014-10-152-5/+4
* i965/fs: Make swizzle_result() not use ir_texture.Connor Abbott2014-10-153-8/+9
* i965/fs: fix integer textures with swizzlesConnor Abbott2014-10-151-0/+1
* i965/fs: don't pass in ir_texture to emit_texture_*Connor Abbott2014-10-153-24/+23
* i965/fs: don't use ir->type in emit_texture_gen4()Connor Abbott2014-10-151-4/+1
* i965/fs: Don't use ir->lod_info.grad.dPd<x,y> in emit_texture_*.Connor Abbott2014-10-153-18/+31
* i965/fs: Don't use ir->coordinate in emit_texture_*.Connor Abbott2014-10-153-31/+39
* i965/fs: make rescale_texcoord() not use ir_texture.Connor Abbott2014-10-153-8/+8
* i965/fs: Make emit_mcs_fetch() not use ir_texture.Connor Abbott2014-10-152-4/+4
* i965/fs: Rename "length" to "components" in emit_mcs_fetch().Kenneth Graunke2014-10-151-6/+6
* i965: Make brw_texture_offset() not use ir_texture.Connor Abbott2014-10-154-12/+15
* i965/fs: don't use ir->offset in emit_texture_gen5.Connor Abbott2014-10-153-5/+8
* i965/fs: Move texel offset handling to visit(ir_texture *).Kenneth Graunke2014-10-153-11/+29
* i965: Drop ir->op != ir_txf condition in offset checking.Kenneth Graunke2014-10-152-4/+3
* i965: Restore a lost comment about TXF offset bugs.Kenneth Graunke2014-10-151-0/+5
* freedreno/ir3: large const supportRob Clark2014-10-155-13/+33
* freedreno: update generated headersRob Clark2014-10-154-5/+10
* freedreno: fix layer_strideRob Clark2014-10-151-1/+1
* freedreno: inline fd_draw_emit()Rob Clark2014-10-152-49/+47
* freedreno/ir3: optimize shader key comparisionRob Clark2014-10-155-40/+79
* freedreno/a3xx: refactor/optimize emitRob Clark2014-10-157-83/+125
* freedreno/a3xx: refactor vertex state emitRob Clark2014-10-1511-79/+83
* vc4: Fix the uniform debug output.Eric Anholt2014-10-151-1/+1
* vc4: Add support for user clip plane and gl_ClipVertex.Eric Anholt2014-10-155-4/+91
* vc4: Move the output semantics setup to a helper.Eric Anholt2014-10-151-16/+28
* i965: Allow CSE on Gen4-5 unary math.Kenneth Graunke2014-10-151-1/+1
* r600g,radeonsi: Only set use_staging_texture = TRUE onceMichel Dänzer2014-10-151-8/+5
* r600g,radeonsi: Use staging texture for transfers if any miplevel is tiledMichel Dänzer2014-10-151-1/+1
* winsys/radeon: Use separate caching buffer manager for each set of flagsMichel Dänzer2014-10-153-41/+32
* configure.ac: check for libexpat when no pkg-config is availableAndres Gomez2014-10-151-8/+7
* clover: Fix regression in module serializationTom Stellard2014-10-141-0/+1
* i965/fs: Use the correct regs_written on unspill instructionsJason Ekstrand2014-10-141-0/+1
* st/gbm: fix order of arguments passed to is_format_supportedIlia Mirkin2014-10-141-1/+1
* nouveau: 3d textures are unsupported, limit 3d levels to 1Ilia Mirkin2014-10-141-0/+3
* freedreno: use tgsi_loweringRob Clark2014-10-148-1673/+6
* r300/compiler: remove useless checkDavid Heidelberger2014-10-141-5/+2
* ilo: Build pipe-loader for iloNick Sarnie2014-10-142-0/+40
* automake: explicitly set TARGET_RADEON_{WINSYS,COMMON}Emil Velikov2014-10-143-5/+5
* vc4: Fix render target NPOT alignment at small miplevels.Eric Anholt2014-10-141-3/+12
* vc4: Add support for having 0 vertex elements used.Eric Anholt2014-10-142-6/+47
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