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* pb: don't keep checking buffers after first busyDave Airlie2010-10-051-13/+19
| | | | | If we assume busy buffers are added to the list in order its unlikely we'd fine one after the first busy one that isn't busy.
* r600g: add bo fenced list.Dave Airlie2010-10-053-0/+43
| | | | | this just keeps a list of bos submitted together, and uses them to decide bo busy state for the whole group.
* swrast: fix choose_depth_texture_level() to respect mipmap filtering stateBrian Paul2010-10-041-5/+10
| | | | NOTE: this is a candidate for the 7.9 branch.
* r300g: fix microtiling for 16-bits-per-channel formatsMarek Olšák2010-10-051-3/+3
| | | | | | These texture formats (like R16G16B16A16_UNORM) were untested until now because st/mesa doesn't use them. I am testing this with a hacked st/mesa here.
* update release notes for GalliumMarek Olšák2010-10-051-4/+19
| | | | | | | | | | I am trying to be exhaustive, but still I might have missed tons of other changes to Gallium. (cherry picked from commit 968a9ec76eadf55e8b58171884e1175d7b8cf59a) Conflicts: docs/relnotes-7.9.html
* docs: Add list of bugs fixed in 7.9Ian Romanick2010-10-041-0/+52
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* i965: Add support for gen6 FB writes to the new FS.Eric Anholt2010-10-042-3/+22
| | | | | This uses message headers for now, since we'll need it for MRT. We can cut out the header later.
* i965: In disasm, gen6 fb writes don't put msg reg # in destreg_conditionalmod.Eric Anholt2010-10-041-1/+1
| | | | It instead sensibly appears in the src0 slot.
* i965: Add initial folding of constants into operand immediate slots.Eric Anholt2010-10-041-0/+90
| | | | | | We could try to detect this in expression handling and do it proactively there, but it seems like less logic to do it in one optional pass at the end.
* i965: Add trivial dead code elimination in the new FS backend.Eric Anholt2010-10-041-2/+50
| | | | | | | The glsl core should be handling most dead code issues for us, but we generate some things in codegen that may not get used, like the 1/w value or pixel deltas. It seems a lot easier this way than trying to work out up front whether we're going to use those values or not.
* i965: Be more conservative on live interval calculation.Eric Anholt2010-10-041-3/+11
| | | | This also means that our intervals now highlight dead code.
* r600g: Fix SCons build.Vinson Lee2010-10-041-1/+1
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* r600g: remove dead label & fix indentationJerome Glisse2010-10-041-11/+9
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: rename radeon_ws_bo to r600_boJerome Glisse2010-10-042-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: use r600_bo for relocation argument, simplify codeJerome Glisse2010-10-044-19/+29
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* r600g: allow r600_bo to be a sub allocation of a big boJerome Glisse2010-10-046-28/+37
| | | | | | | Add bo offset everywhere needed if r600_bo is ever a sub bo of a bigger bo. Signed-off-by: Jerome Glisse <[email protected]>
* r600g: rename radeon_ws_bo to r600_boJerome Glisse2010-10-0412-86/+86
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* nvfx: Pair os_malloc_aligned() with os_free_aligned().Krzysztof Smiechowicz2010-10-041-1/+1
| | | | From AROS.
* r600g: TODO domain managementDave Airlie2010-10-041-2/+2
| | | | | no wonder it was slow, the code is deliberately forcing stuff into GTT, we used to have domain management but it seems to have disappeared.
* r600g: fix wwarning in bo_map functionDave Airlie2010-10-041-0/+1
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* r600g: the code to check whether a new vertex shader is needed was wrongDave Airlie2010-10-041-1/+3
| | | | | | | this code was memcmp'ing two structs, but refcounting one of them afterwards, so any subsequent memcmp was never going to work. again this stops unnecessary uploads of vertex program,
* r600g: break out of search for reloc bo after finding it.Dave Airlie2010-10-041-0/+1
| | | | this function was taking quite a lot of pointless CPU.
* i965: Fix glean/texSwizzle regression in previous commit.Eric Anholt2010-10-031-18/+18
| | | | Easy enough patch, who needs a full test run. Oh, that's right. Me.
* i965: Set up swizzling of shadow compare results for GL_DEPTH_TEXTURE_MODE.Eric Anholt2010-10-021-1/+32
| | | | | | | | | | The brw_wm_surface_state.c handling of GL_DEPTH_TEXTURE_MODE doesn't apply to shadow compares, which always return an intensity value. The texture swizzles can do the job for us. Fixes: glsl1-shadow2D(): 1 glsl1-shadow2D(): 3
* i965: Add support for EXT_texture_swizzle to the new FS backend.Eric Anholt2010-10-021-0/+21
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* r300g: add support for L8A8 colorbuffersMarek Olšák2010-10-021-0/+3
| | | | | Blending with DST_ALPHA is undefined. SRC_ALPHA works, though. I bet some other formats have similar limitations too.
* r300g: add support for R8G8 colorbuffersMarek Olšák2010-10-021-1/+11
| | | | | | | | The hw swizzles have been obtained by a brute force approach, and only C0 and C2 are stored in UV88, the other channels are ignored. R16G16 is going to be a lot trickier.
* mesa/st: initial attempt at RG support for gallium driversDave Airlie2010-10-024-1/+93
| | | | passes all piglit RG tests with softpipe.
* i965: Fix incorrect batchbuffer size in gen6 clip state command.Kenneth Graunke2010-10-011-1/+0
| | | | FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
* i965: Don't try to emit code if we failed register allocation.Eric Anholt2010-10-011-1/+2
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* i965: Fix off-by-ones in handling the last members of register classes.Eric Anholt2010-10-011-5/+5
| | | | | | | Luckily, one of them would result in failing out register allocation when the other bugs were encountered. Applies to glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still fails register allocation, but now legitimately.
* i965: Add a sanity check for register allocation sizes.Eric Anholt2010-10-011-0/+5
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* i965: When producing a single channel swizzle, don't make a temporary.Eric Anholt2010-10-011-0/+5
| | | | This quickly cuts 8% of the instructions in my glsl demo.
* i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.Eric Anholt2010-10-011-12/+43
| | | | | By doing so using the register allocator now, we avoid wasting a register to make the alignment happen.
* r600c: fix segfault in evergreen stencil codeAlex Deucher2010-10-011-15/+9
| | | | | Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=30551
* r600g: Remove unnecessary headers.Vinson Lee2010-10-012-3/+0
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* r600g: Remove unused variable.Vinson Lee2010-10-011-1/+1
| | | | | | Fixes this GCC warning. r600_shader.c: In function 'tgsi_split_literal_constant': r600_shader.c:818: warning: unused variable 'index'
* rgtc: Detect RGTC formats as color formats and as compressed formatsIan Romanick2010-10-011-0/+9
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* mesa: Trivial correction to commentIan Romanick2010-10-011-1/+1
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* mesa: Fix misplaced #endifIan Romanick2010-10-011-1/+1
| | | | | If FEATURE_texture_s3tc is not defined, FXT1 formats would erroneously fall through to the MESA_FORMAT_RGBA_FLOAT32 case.
* ARB_texture_rg: Add GL_COMPRESSED_{RED,RG} cases in _mesa_is_color_formatIan Romanick2010-10-011-0/+2
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* mesa: Add ARB_texture_compression_rgtc as an alias for ↵Ian Romanick2010-10-014-8/+9
| | | | | | EXT_texture_compression_rgtc Change the name in the extension tracking structure to ARB (from EXT).
* savage: Remove unnecessary header.Vinson Lee2010-10-011-1/+0
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* glsl: Remove unnecessary header.Vinson Lee2010-10-011-1/+0
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* i965: Enable GL_ARB_texture_rgIan Romanick2010-10-014-0/+91
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* mesa: Enable GL_ARB_texture_rg in software pathsIan Romanick2010-10-011-0/+1
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* ARB_texture_rg: Allow RED and RG textures as FBO color buffer attachmentsIan Romanick2010-10-011-2/+8
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* ARB_texture_rg: Add R8, R16, RG88, and RG1616 internal formatsIan Romanick2010-10-018-30/+515
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* ARB_texture_rg: Handle RED and RG the same as RGB for tex envIan Romanick2010-10-011-0/+6
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* ARB_texture_rg: Add GL_RED as a valid GL_DEPTH_TEXTURE_MODEIan Romanick2010-10-012-1/+5
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