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* main: Added entry point for glTextureParameteri.Laura Ekstrand2015-01-082-11/+52
* main: Added entry point for glTextureParameterfv.Laura Ekstrand2015-01-084-13/+59
* main: Added entry point for glTextureParameterf.Laura Ekstrand2015-01-084-10/+66
* main: Added get_texobj_by_name in texparam.c.Laura Ekstrand2015-01-081-13/+51
* main: set_tex_parameterf now handles errors according to the OpenGL 4.5 Speci...Laura Ekstrand2015-01-081-17/+20
* main: set_tex_parameteri now handles errors according to the OpenGL 4.5 Speci...Laura Ekstrand2015-01-081-28/+42
* main: Added entry point for BindTextureUnit.Laura Ekstrand2015-01-086-5/+155
* main: Corrected comment on _mesa_is_zero_size_texture.Laura Ekstrand2015-01-081-1/+1
* main: Added entry points for glTextureSubImage*D.Laura Ekstrand2015-01-084-81/+320
* main: Added entry points for glTextureStorage*D.Laura Ekstrand2015-01-084-51/+213
* main: Added entry point for glCreateTextures.Laura Ekstrand2015-01-084-26/+98
* main: Removed trailing whitespaces in texture code.Laura Ekstrand2015-01-082-28/+28
* main: Renamed _mesa_get_compressed_teximage to _mesa_GetCompressedTexImage_sw.Laura Ekstrand2015-01-084-8/+8
* main: Renamed _mesa_get_teximage to _mesa_GetTexImage_sw.Laura Ekstrand2015-01-084-12/+12
* main: Changed _mesa_alloc_texture_storage to _mesa_AllocTextureStorage_sw.Laura Ekstrand2015-01-084-10/+10
* main: Moved _mesa_get_current_tex_object from teximage.c to texobj.c.Laura Ekstrand2015-01-084-85/+84
* main: Moved _mesa_lock_texture and _mesa_unlock_texture to texobj.h from texi...Laura Ekstrand2015-01-085-19/+21
* i965: blit_texture_to_pbo() now accepts TEXTURE_CUBE_MAP.Laura Ekstrand2015-01-081-0/+1
* main: Added utility function _mesa_lookup_texture_err().Laura Ekstrand2015-01-082-0/+19
* glapi: Added ARB_direct_state_access.xml file.Laura Ekstrand2015-01-084-1/+18
* st/wgl: Ignore ulVersion in DrvValidateVersion.José Fonseca2015-01-081-2/+10
* mesa: Address `assignment makes integer from pointer without a cast` gcc warn...José Fonseca2015-01-081-2/+2
* i965/skl: Always use a header for SIMD4x2 sampler messagesKristian Høgsberg2015-01-085-11/+54
* i965/skl: Report more accurate number of samples for formatKristian Høgsberg2015-01-071-0/+2
* freedreno/ir3: fix pos_regid > max_regRob Clark2015-01-074-41/+121
* freedreno/ir3: start on indirect gpr readsRob Clark2015-01-073-8/+146
* freedreno/ir3: make reg array dynamicRob Clark2015-01-074-13/+50
* freedreno/ir3: simplify RARob Clark2015-01-078-777/+622
* freedreno/ir3: regmask support for relative addrRob Clark2015-01-072-17/+51
* freedreno/ir3: split up ssa_srcRob Clark2015-01-071-23/+34
* freedreno/ir3: drop instr_clone() stuffRob Clark2015-01-072-49/+17
* freedreno/ir3: runtime enable RA debug for DEBUG buildsRob Clark2015-01-071-1/+6
* freedreno/ir3: handle relative addr in ir3_dumpRob Clark2015-01-071-1/+8
* freedreno/ir3: legalize vs unused sam dst componentsRob Clark2015-01-072-2/+9
* freedreno/ir3: hack for old compilerRob Clark2015-01-071-0/+23
* tgsi: track max array per fileRob Clark2015-01-072-0/+4
* tgsi: keep track of read vs written indirectsRob Clark2015-01-072-0/+8
* Revert "radeonsi: reduce the size of si_pm4_state"Marek Olšák2015-01-082-3/+12
* radeonsi: Fix crash when destroying si_screenTom Stellard2015-01-071-2/+4
* mesa: Don't use _mesa_generic_nop on Windows.José Fonseca2015-01-071-0/+9
* glapi: Force frame pointer elimination on Windows.José Fonseca2015-01-071-0/+22
* radeonsi: enable LLVM optimizations that assume no NaNs for non-compute shadersMarek Olšák2015-01-073-4/+12
* radeonsi: emit SURFACE_SYNC lastMarek Olšák2015-01-071-23/+35
* radeonsi: flush all CB/DB caches unconditionally when changing the framebufferMarek Olšák2015-01-071-11/+7
* radeonsi: change TC cache flushing strategy for texturesMarek Olšák2015-01-072-4/+6
* radeonsi: improve and fix streamout flushingMarek Olšák2015-01-073-10/+40
* radeonsi: use TC L2 for CP DMA operations with shader resources on CIKMarek Olšák2015-01-073-10/+39
* radeonsi: use TC L2 for updating descriptors on CIKMarek Olšák2015-01-072-5/+10
* radeonsi: don't use TC L2 for updating descriptors on SIMarek Olšák2015-01-072-2/+14
* radeonsi: only flush the right set of caches for CP DMA operationsMarek Olšák2015-01-079-34/+48
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