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* glx: move 'prime' var into #ifdef'd code blockBrian Paul2012-09-061-8/+10
| | | | | | To silence unused var warning. Reviewed-by: Jose Fonseca <[email protected]>
* i965: Fix primitive restart on Haswell.Kenneth Graunke2012-09-065-1/+43
| | | | | | | | | | | | | | | | | | | | | Haswell moved the "Cut Index Enable" bit from the INDEX_BUFFER packet to a new 3DSTATE_VF packet, so we need to emit that. Also, it requires us to specify the cut index rather than assuming it's 0xffffffff. This adds a new Haswell-specific tracked state atom to gen7_atoms. Normally, we would create a new generation-specific atom list, but since there's only one difference over Ivybridge so far, I chose to simply make it return without doing any work on non-Haswell systems. Fixes five piglit tests: - general/primitive-restart-DISABLE_VBO - general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX - general/primitive-restart-VBO_INDEX_ONLY - general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX - general/primitive-restart-VBO_VERTEX_ONLY Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* build: Disable building of d3d1xMatt Turner2012-09-061-5/+7
| | | | | It's broken and unmaintained, and I'm tired of seeing bug reports about it.
* intel: avoid undefined variable warnings in intel_screen.cPaul Berry2012-09-061-2/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* r600g: order atom emission v3Jerome Glisse2012-09-067-82/+116
| | | | | | | | | | | | | To avoid GPU lockup registers must be emited in a specific order (no kidding ...). This patch rework atom emission so order in which atom are emited in respect to each other is always the same. We don't have any informations on what is the correct order so order will need to be infered from fglrx command stream. v2: add comment warning that atom order should not be taken lightly v3: rebase on top of alphatest atom fix Signed-off-by: Jerome Glisse <[email protected]>
* r600g: fix num of dwords needed for alphatest_state atomJerome Glisse2012-09-061-1/+1
| | | | Signed-off-by: Jerome Glisse <[email protected]>
* mesa: Don't advertise GLES extensions in GL contextsChad Versace2012-09-061-5/+6
| | | | | | | | | | | | glGetStringi(GL_EXTENSIONS) failed to respect the context's API, and so returned all internally enabled GLES extensions from a GL context. Likewise, glGetIntegerv(GL_NUM_EXTENSIONS) also failed to repsect the context's API. Note: This is a candidate for the 8.0 and 9.0 branches. Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* llvmpipe: Make driver name more informative.José Fonseca2012-09-061-1/+4
| | | | | | | | | | | | | | | Such as "llvmpipe (LLVM 3.1, 128 bits)" or "llvmpipe (LLVM 3.1, 256 bits)" when leveraging AVX 8-wide registers. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* radeonsi: Handle more L/I/A format cases.Michel Dänzer2012-09-061-0/+14
| | | | | | | Fixes piglit fbo-generatemipmap-formats. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Enable whole quad mode for pixel shaders.Michel Dänzer2012-09-061-2/+10
| | | | | | | Fixes wrong mipmap level being sampled at some triangle edges. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.Michel Dänzer2012-09-064-0/+23
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: SI shader vector instructions implicitly use the EXEC register.Michel Dänzer2012-09-061-0/+4
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Extend SI EXEC register support.Michel Dänzer2012-09-062-2/+7
| | | | | | | Add 32 bit lo and hi variants, and binary encodings. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: Remove R600InstrInfo.td from TD_FILESTom Stellard2012-09-061-1/+0
| | | | | Fixes build bug introduced by cebbdd4ac23725963207bf6f8fc7101150e6065f
* radeonsi: Enable NPOT textures again.Michel Dänzer2012-09-061-1/+1
| | | | | | | | Should be at least mostly working now (with the corresponding fixes in libdrm_radeon). Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Mipmaps require memory footprint to be padded to powers of two.Michel Dänzer2012-09-061-0/+1
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Sampler view state simplification.Michel Dänzer2012-09-061-11/+9
| | | | | | | | We can always use the offset and tiling mode from level 0 and restrict the first and last mipmap level to be used in the sampler resource. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeonsi: Untiled textures are linear aligned, not linear general.Michel Dänzer2012-09-061-3/+3
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]>
* radeon/llvm: Cleanup makefileTom Stellard2012-09-062-13/+37
| | | | | Hopefully, this will fix all the parallel make problems people have been having.
* Remove useless checks for NULL before freeingMatt Turner2012-09-0528-115/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Same as earlier commit, except for "FREE" This patch has been generated by the following Coccinelle semantic patch: // Remove useless checks for NULL before freeing // // free (NULL) is a no-op, so there is no need to avoid it @@ expression E; @@ + FREE (E); + E = NULL; - if (unlikely (E != NULL)) { - FREE(E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; type T; @@ + FREE ((T) E); + E = NULL; - if (unlikely (E != NULL)) { - FREE((T) E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; @@ + FREE (E); - if (unlikely (E != NULL)) { - FREE (E); - } @@ expression E; type T; @@ + FREE ((T) E); - if (unlikely (E != NULL)) { - FREE ((T) E); - } Reviewed-by: Brian Paul <[email protected]>
* Replace another malloc/memset-0 combination with callocMatt Turner2012-09-051-2/+1
| | | | Reviewed-by: Brian Paul <[email protected]>
* Remove useless memset after callocMatt Turner2012-09-052-2/+0
| | | | Reviewed-by: Brian Paul <[email protected]>
* Use calloc instead of malloc/memset-0Matt Turner2012-09-059-41/+18
| | | | | | | | | | | | | | | | This patch has been generated by the following Coccinelle semantic patch: @@ expression E; identifier I; @@ - I = malloc(E); + I = calloc(1, E); ... - memset(I, 0, sizeof *I); Reviewed-by: Brian Paul <[email protected]>
* Remove useless checks for NULL before freeingMatt Turner2012-09-0546-184/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has been generated by the following Coccinelle semantic patch: // Remove useless checks for NULL before freeing // // free (NULL) is a no-op, so there is no need to avoid it @@ expression E; @@ + free (E); + E = NULL; - if (unlikely (E != NULL)) { - free(E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; type T; @@ + free ((T) E); + E = NULL; - if (unlikely (E != NULL)) { - free((T) E); ( - E = NULL; | - E = 0; ) ... - } @@ expression E; @@ + free (E); - if (unlikely (E != NULL)) { - free (E); - } @@ expression E; type T; @@ + free ((T) E); - if (unlikely (E != NULL)) { - free ((T) E); - } Reviewed-by: Brian Paul <[email protected]>
* glX_proto_send.py: Don't cast the return value of mallocMatt Turner2012-09-051-1/+1
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* Don't cast the return value of malloc/reallocMatt Turner2012-09-0593-221/+217
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has been generated by the following Coccinelle semantic patch: // Don't cast the return value of malloc/realloc. // // Casting the return value of malloc/realloc only stands to hide // errors. @@ type T; expression E1, E2; @@ - (T) ( _mesa_align_calloc(E1, E2) | _mesa_align_malloc(E1, E2) | calloc(E1, E2) | malloc(E1) | realloc(E1, E2) )
* glX_proto_send.py: Remove deprecated Xmalloc/Xfree callsMatt Turner2012-09-051-3/+3
| | | | Reviewed-by: Brian Paul <[email protected]>
* Remove Xcalloc/Xmalloc/Xfree callsMatt Turner2012-09-0531-192/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These calls allowed Xlib to use a custom memory allocator, but Xlib has used the standard C library functions since at least its initial import into git in 2003. It seems unlikely that it will grow a custom memory allocator. The functions now just add extra overhead. Replacing them will make future Coccinelle patches simpler. This patch has been generated by the following Coccinelle semantic patch: // Remove Xcalloc/Xmalloc/Xfree calls @@ expression E1, E2; @@ - Xcalloc (E1, E2) + calloc (E1, E2) @@ expression E; @@ - Xmalloc (E) + malloc (E) @@ expression E; @@ - Xfree (E) + free (E) @@ expression E; @@ - XFree (E) + free (E) Reviewed-by: Brian Paul <[email protected]>
* Use the correct macro _WIN32 for Windows.Vinson Lee2012-09-0514-20/+20
| | | | | | | | | | | | | | The correct predefined macro for Windows is _WIN32, not WIN32 or __WIN32__. _WIN32 is defined for 32-bit and 64-bit version of Windows by both MSVC and MinGW compilers. http://sourceforge.net/p/predef/wiki/OperatingSystems http://msdn.microsoft.com/en-us/library/b0084kay.aspx This patch also fixes a MinGW automake build error. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: remove #undef CONST in get.cBrian Paul2012-09-051-2/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: remove now unused CONST macroBrian Paul2012-09-051-11/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: s/CONST/const/ in a commentBrian Paul2012-09-051-3/+3
| | | | Reviewed-by: Matt Turner <[email protected]>
* mesa: s/CONST/const/ in math/ filesBrian Paul2012-09-054-42/+42
| | | | | | The CONST macro hack will go away soon. Reviewed-by: Matt Turner <[email protected]>
* radeon/llvm: Fix operand ordering for V_CNDMASK_B32Tom Stellard2012-09-051-3/+3
| | | | This fixes several hundred piglit tests.
* radeon/llvm: Use correct float->int conversion opcode on SI.Tom Stellard2012-09-051-2/+4
| | | | | V_CVT_I32_F32 converts floats to signed integers, but we were using V_CVT_F32_I32 which convertes signed integers to float.
* configure.ac: Don't link gallium drivers with libdricoreTom Stellard2012-09-051-1/+0
| | | | Reviewed-by: Matt Turner <[email protected]>
* i965/blorp: Fix incorrect indentation.Paul Berry2012-09-051-2/+2
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* mapi: Add shared-glapi-test to .gitignorePaul Berry2012-09-051-0/+1
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* mesa: fix per-level max texture size error checkingBrian Paul2012-09-051-15/+21
| | | | | | | | | | | | | This is a long-standing omission in Mesa's texture image size checking. We need to take the mipmap level into consideration when checking if the width, height and depth are too large. Fixes the new piglit max-texture-size-level test. Thanks to Stéphane Marchesin for finding this problem. Note: This is a candidate for the stable branches. Reviewed-by: Michel Dänzer <[email protected]>
* i965: Don't use brw->fragment_program in the old brw_wm_pass2.c.Kenneth Graunke2012-09-051-1/+1
| | | | | | | | | | | | | | According to Eric, this shouldn't matter since we don't do precompiles using the old backend. In other words, brw->fragment_program (the currently active program) should equal c->fp (the program currently being compiled). However, it's just not a good idea to access brw->fragment_program directly in compiler code. It's totally illegal in the new backend, so let's just not do it here either. Signed-off-by: Kenneth Graunke <[email protected]> Reported-by: Paul Berry <[email protected]>
* radeon/llvm: Fix lowering of SI_V_CNDLTTom Stellard2012-09-041-3/+3
| | | | | SREG_LIT_0 is a scalar register, so it can only be used in the first argument of vector instructoins.
* radeon/llvm: Fix encoding of V_CNDMASK_B32Tom Stellard2012-09-042-4/+4
| | | | | | | The CodeEmitter was not setting the VGPR bit for src0, because the instruction definition had the VCC register in the src0 slot, instead of the actual src0 register. This has been fixed by moving the VCC register to the end of the operand list.
* mesa: fix DIFFERENT_SIGNS() functionBrian Paul2012-09-041-1/+1
| | | | | | | | | | Looks like converting this to a macro, returning bool, caused us to lose the high (31st) bit result. Fixes piglit fbo-1d test. Strange that none of the other tests I ran caught this. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=54365 Tested-by: Vinson Lee <[email protected]>
* radeon/llvm: do not convert f32 operand of select_cc nodeVincent Lejeune2012-09-041-20/+20
| | | | | | v2:-use camel coding style Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)Vincent Lejeune2012-09-042-2/+26
| | | | | | v2:-wrap line at 80 characters Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: support setcc on f32Vincent Lejeune2012-09-041-9/+27
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radon/llvm: br_cc f32 now lowered without castVincent Lejeune2012-09-041-9/+24
| | | | Reviewed-by: Tom Stellard <[email protected]>
* radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and useVincent Lejeune2012-09-042-4/+4
| | | | Reviewed-by: Tom Stellard <[email protected]>
* winsys/radeon: create only one winsys for each fdChristian König2012-09-042-2/+41
| | | | | | | Fixing problems with GLAMOR. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: stop big offsets from hanging the GPU v2Christian König2012-09-041-2/+9
| | | | | | | v2: rebased of radeon/llvm fix. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
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