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* radeonsi: implement uniform buffer objectsMarek Olšák2013-11-044-31/+41
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* tgsi/scan: set maximum index for each constant bufferMarek Olšák2013-11-042-1/+13
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* radeonsi: try to fix IA_MULTI_VGT_PARAM programmingMarek Olšák2013-11-043-2/+8
| | | | This doesn't make any difference on Bonaire, but it might help on Hawaii.
* winsys/radeon: use type-3 NOPs for CS padding on CIKMarek Olšák2013-11-041-2/+7
| | | | The type-2 NOPs are said to be unstable. It doesn't make a difference here.
* clover: fix build with LLVM 3.4Aaron Watry2013-11-041-5/+0
| | | | | | | | dso_list was added as an argument for createInternalizePass in 3.4, and then it was removed again in the same llvm version. Tested-by: Mike Lothian <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* draw: move type construction out of loopBrian Paul2013-11-041-1/+3
| | | | | | We can create clip_ptr_type once instead of n times inside the loop. Reviewed-by: Roland Scheidegger <[email protected]>
* i965: Add driconf option clamp_max_samplesChad Versace2013-11-032-12/+67
| | | | | | | | | | | | | | | | | | | | The new option clamps GL_MAX_SAMPLES to a hardware-supported MSAA mode. If negative, then no clamping occurs. v2: (for Paul) - Add option to i965 only, not to all DRI drivers. - Do not realy on int->uint cast to convert negative values to large positive values. Explicitly check for clamp_max_samples < 0. v3: (for Ken) - Don't allow clamp_max_samples to alter context version. - Use clearer for-loop and correct comment. - Rename variables. v4: (for Ken) - Merge identical if-branches. Reviewed-and-tested-by: Kenneth Graunke <[email protected]> Signed-off-by: Chad Versace <[email protected]>
* i965: Fix logic_op check.Vinson Lee2013-11-031-2/+1
| | | | | | | Fixes "Macro compares unsigned to 0" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i915: Fix logic_op check.Vinson Lee2013-11-031-2/+1
| | | | | | | Fixes "Macro compares unsigned to 0" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Initialize vec4_visitor member variables.Vinson Lee2013-11-031-1/+6
| | | | | | | Fixes "Uninitialized pointer field" defect reported by Coverity. Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* gallium/targets: remove vdpau-softpipeMarek Olšák2013-11-023-84/+0
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove xvmc-softpipeMarek Olšák2013-11-023-80/+0
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove r300/vdpauMarek Olšák2013-11-023-80/+1
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove r300/xvmcMarek Olšák2013-11-023-75/+1
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove radeonsi/xorgMarek Olšák2013-11-024-222/+1
| | | | Reviewed-by: Christian König <[email protected]>
* gallium/targets: remove r600/xorgMarek Olšák2013-11-024-228/+1
| | | | Reviewed-by: Christian König <[email protected]>
* freedreno/a3xx/texture: min/max lodRob Clark2013-11-011-5/+3
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: update envytools headersRob Clark2013-11-014-8/+22
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: fix VS out / FS in linkingRob Clark2013-11-013-7/+47
| | | | | | | | Actually link VS out / FS in based on semantic info, keeping in mind that position/pointsize can also be an input to the FS. This fixes a few fragment shaders which were using gl_Position. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx: allow num_samplers != num_texturesRob Clark2013-11-012-56/+55
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: highp frag shaderRob Clark2013-11-014-12/+14
| | | | | | | | | | | | | | Fixes use of full-precision in fragment shader (ie. don't clobber r0.x since that can be used by future bary instructions for varying fetch). And makes use of full-precision the default in fragment shader (but can be overriden via FD_MESA_DEBUG=fraghalf). Seems like half precision is often not enough for texture coordinates. The blob compiler is clever enough to keep texture coords in full precision registers while using half precision for everything else. But we aren't quite that clever yet, so better to default to full precision. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx/compiler: relative addressing fixes.Rob Clark2013-11-011-28/+48
| | | | | | | Handle some relative addressing constraints: cannot handle const or relative in cat5 and src2 of cat3. Signed-off-by: Rob Clark <[email protected]>
* freedreno: we do actually support sqrtRob Clark2013-11-012-0/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* i965: Enable ARB_sample_shading on intel hardware >= gen6Anuj Phogat2013-11-011-0/+1
| | | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ken Graunke <[email protected]>
* i965/gen7: Enable the features required for GL_ARB_sample_shadingAnuj Phogat2013-11-011-5/+56
| | | | | | | | | | | | | | | | | | | | - Enable GEN7_WM_MSDISPMODE_PERSAMPLE, GEN7_WM_POSOFFSET_SAMPLE, GEN7_WM_OMASK_TO_RENDER_TARGET as per extension's specification. - Only enable one of GEN7_WM_8_DISPATCH_ENABLE or GEN7_WM_16_DISPATCH_ENABLE when GEN7_WM_MSDISPMODE_PERSAMPLE is enabled. Refer IVB PRM Vol. 2, Part 1, Page 288 for details. V2: - Use shared function _mesa_get_min_invocations_per_fragment(). - Use brw_wm_prog_data variables: uses_pos_offset, uses_omask. V3: - Enable simd16 dispatch with per sample shading. - Make changes to give preference to 'simd16 only' mode over 'simd8 only' mode in case of non 1x per sample shading. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/gen6: Enable the features required for GL_ARB_sample_shadingAnuj Phogat2013-11-011-5/+56
| | | | | | | | | | | | | | | | | | | | - Enable GEN6_WM_MSDISPMODE_PERSAMPLE, GEN6_WM_POSOFFSET_SAMPLE, GEN6_WM_OMASK_TO_RENDER_TARGET as per extension's specification. - Only enable one of GEN6_WM_8_DISPATCH_ENABLE or GEN6_WM_16_DISPATCH_ENABLE when GEN6_WM_MSDISPMODE_PERSAMPLE is enabled. Refer SNB PRM Vol. 2, Part 1, Page 279 for details. V2: - Use shared function _mesa_get_min_invocations_per_fragment(). - Use brw_wm_prog_data variables: uses_pos_offset, uses_omask. V3: - Enable simd16 dispatch with per sample shading. - Make changes to give preference to 'simd16 only' mode over 'simd8 only' mode in case of non 1x per sample shading. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add FS backend for builtin gl_SampleMask[]Anuj Phogat2013-11-015-0/+61
| | | | | | | | | | | | | | V2: - Update comments - Add a special backend instructions to compute sample_mask. - Add a new variable uses_omask in brw_wm_prog_data. V3: - Make changes to support simd16 mode. - Delete redundant AND instruction and handle the register stride in FS backend instruction. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add FS backend for builtin gl_SampleIDAnuj Phogat2013-11-017-0/+94
| | | | | | | | | | | | | V2: - Update comments - Add compute_sample_id variables in brw_wm_prog_key - Add a special backend instruction to compute sample_id. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Add FS backend for builtin gl_SamplePositionAnuj Phogat2013-11-016-0/+95
| | | | | | | | | | | | | V2: - Update comments. - Add compute_pos_offset variable in brw_wm_prog_key. - Add variable uses_pos_offset in brw_wm_prog_data. V3: - Make changes to support simd16 mode. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965: Don't do vector splitting for ir_var_system_valueAnuj Phogat2013-11-011-0/+1
| | | | | | | | | | | | | This is required while adding builtin system value vec{2, 3, 4} variables. For example: (declare (sys) vec2 gl_SamplePosition) Without this patch above glsl ir splits in to: (declare (temporary) float gl_SamplePosition_x) (declare (temporary) float gl_SamplePosition_y) Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: Add a helper function _mesa_get_min_invocations_per_fragment()Anuj Phogat2013-11-012-0/+35
| | | | | | | | | | | This function is used to test if we need to do per sample shading or per fragment shading. V2: Use MAX2() to make sure the function returns a number >= 1. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* glsl: Add new builtins required by GL_ARB_sample_shadingAnuj Phogat2013-11-013-1/+28
| | | | | | | | | | | | | | | | New builtins added by GL_ARB_sample_shading: in vec2 gl_SamplePosition in int gl_SampleID in int gl_NumSamples out int gl_SampleMask[] V2: - Use SWIZZLE_XXXX for STATE_NUM_SAMPLES. - Use "result.samplemask" in arb_output_attrib_string. - Add comment to explain the size of gl_SampleMask[] array. - Make gl_SampleID and gl_SamplePosition system values. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Pass number of samples as a program state variableAnuj Phogat2013-11-012-0/+13
| | | | | | | | | | | | | Number of samples will be required in fragment shader program by new GLSL builtin uniform "gl_NumSamples". V2: Use "state.numsamples" in place of "state.num.samples" Use _NEW_BUFFERS flag in place of _NEW_MULTISAMPLE Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Ken Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* mesa: Add new functions and enums required by GL_ARB_sample_shadingAnuj Phogat2013-11-0111-4/+100
| | | | | | | | | | | | | | | | | | | | | | New functions added by GL_ARB_sample_shading: glMinSampleShadingARB() New enums: GL_SAMPLE_SHADING_ARB GL_MIN_SAMPLE_SHADING_VALUE_ARB V2: Update comments. Create new GL4x.xml. Remove redundant code in get.c. Update the API_XML list in Makefile.am. Add extra_gl40_ARB_sample_shading predicate to get.c. V3: Fix make check failure. Add checks for desktop GL. Use GLfloat in place of GLclampf in glMinSampleShading(). Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ken Graunke <[email protected]>
* mesa: Add infrastructure for GL_ARB_sample_shadingAnuj Phogat2013-11-016-0/+9
| | | | | | | | | | | This patch implements the common support code required for the GL_ARB_sample_shading extension. V2: Move GL_ARB_sample_shading to ARB extension list. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Ken Graunke <[email protected]>
* i965/fs: Optimize saturating SEL.G(E) with imm val <= 0.0f.Matt Turner2013-11-011-0/+14
| | | | | | | | | | Only one program's instruction count is changed, but a shader in Tropics is also affected. instructions in affected programs: 326 -> 320 (-1.84%) Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Optimize saturating SEL.L(E) with imm val >= 1.0.Matt Turner2013-11-011-0/+22
| | | | | | | | total instructions in shared programs: 1409124 -> 1406971 (-0.15%) instructions in affected programs: 158376 -> 156223 (-1.36%) Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* i965/fs: Optimize OR with identical sources into a MOV.Matt Turner2013-11-011-0/+8
| | | | | | | | | | Helps a lot of Steam games. total instructions in shared programs: 1409360 -> 1409124 (-0.02%) instructions in affected programs: 20842 -> 20606 (-1.13%) Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Paul Berry <[email protected]>
* glsl: Add a CSE pass.Eric Anholt2013-11-015-0/+608
| | | | | | | | | | | | | | | | | | | | | | | | This only operates on constant/uniform values for now, because otherwise I'd have to deal with killing my available CSE entries when assignments happen, and getting even this working in the tree ir was painful enough. As is, it has the following effect in shader-db: total instructions in shared programs: 1524077 -> 1521964 (-0.14%) instructions in affected programs: 50629 -> 48516 (-4.17%) GAINED: 0 LOST: 0 And, for tropics, that accounts for most of the effect, the FPS improvement is 11.67% +/- 0.72% (n=3). v2: Use read_only field of the variable, manually check the lod_info union members, use get_num_operands(), rename cse_operands_visitor to is_cse_candidate_visitor, move all is-a-candidate logic to that function, and call it before checking for CSE on a given rvalue, more comments, use private keyword. Reviewed-by: Paul Berry <[email protected]>
* i965/vec4: Don't overwrite op[1] when doing a UBO load.Eric Anholt2013-11-011-2/+3
| | | | | | | | | | | | | Prior to the GLSL CSE pass, all of our testing happened to have a freshly computed temporary in op[1], from the multiply by 16 to get a byte offset. As of CSE you'll get var_refs of a reused value when you've got multiple loads from the same offset. Make a proper temporary for computing our temporary value, to avoid shifting the value farther and farther down. Avoids a regression in gs-float-array-variable-index Reviewed-by: Paul Berry <[email protected]>
* st/mesa: fix _mesa_init_transform_feedback_object() argumentBrian Paul2013-11-011-1/+1
| | | | | Need to pass a pointer of the base type, not the st type. Fixes a compiler warning.
* i965: Fix brw_store_register_mem64 to stay within a single batch.Kenneth Graunke2013-10-311-4/+1
| | | | | | | | Previously, the write of each 32-bit half might land in separate batch buffers, which is insane. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* docs: List transfom_feedback{2,3,instanced} for i965 in release notes.Kenneth Graunke2013-10-311-0/+1
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* i965: Enable the ARB_transform_feedback_instanced extension on Gen7+.Kenneth Graunke2013-10-311-0/+1
| | | | | | | | | | | This depends on ARB_transform_feedback2, so I've predicated it on the ability to do register writes. It also depends on ARB_transform_feedback3, which is the only reason we couldn't expose it previously. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Enable the ARB_transform_feedback3 extension on Gen7+.Kenneth Graunke2013-10-311-0/+1
| | | | | | | | | | | | | | | | | | | | This extension is written a bit strangely. Although it introduces the concept of multiple transform feedback streams, it doesn't actually provide more than a single stream. The ARB_gpu_shader5 extension is what introduces the ability to write to streams other than stream #0 and increases the required number of streams. Since we don't yet support ARB_gpu_shader5, we can safely enable ARB_transform_feedback3 even though we only support a single stream. This does provide some useful functionality: applications can now use more than one interleaved transform feedback buffer. v2: Only expose the extension if ARB_transform_feedback2 is also available, to avoid confusing applications (suggested by Ian). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Add support for gl_SkipComponents[1234].Kenneth Graunke2013-10-311-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | ARB_transform_feedback3 allows applications to insert blank space between interleaved varyings by adding fake 1, 2, 3, or 4-component varyings named gl_SkipComponents[1234]. Mesa's core data structures don't explicitly track these, instead simply tracking the buffer offset for each real varying. If there is padding due to gl_SkipComponents, these will not be contiguous. Our hardware takes the specification quite literally. Instead of specifying offsets for each varying, it assumes they're all contiguous and requires you to program fake varyings for each "hole". This patch adds support for emitting SO_DECL structures for these holes. Although we've lost the information about exactly how the application specified their padding (i.e. gl_SkipComponents2, gl_SkipComponents2 vs. a single gl_SkipComponents4), it shouldn't matter. We just need to emit the right amount of space. This patch emits the minimal number of hole SO_DECL structures. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Explicitly maintain a count of SO_DECL structures emitted.Kenneth Graunke2013-10-311-8/+7
| | | | | | | | | | | | | Currently, we emit one SO_DECL structure per output, so we use the index in the Outputs[] array as the index into the so_decl[] array as well. In order to support the fake "gl_SkipComponents[1234]" varyings from ARB_transform_feedback3, we'll need to emit SO_DECLs to fill in the holes between successive outputs. This means we'll likely emit more SO_DECLs than there are outputs, so we need to count it explicitly. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Create a temporary for transform feedback output components.Kenneth Graunke2013-10-311-4/+4
| | | | | | | | | This is a bit shorter. v2: Mark the temporary const (requested by Ian). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965: Enable ARB_transform_feedback2 on Gen7+ if register writes work.Kenneth Graunke2013-10-311-1/+61
| | | | | | | | | | | | With Linux 3.12, register writes work on Ivybridge and Baytrail, but not Haswell. That will be fixed in a future kernel revision, at which point this extension will automatically be enabled. v2: Use I915_GEM_DOMAIN_INSTRUCTION for the register read, and also correctly set the writeable flag when mapping (caught by Eric). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* i965: Initialize batchbuffer and state modules before extensions.Kenneth Graunke2013-10-311-4/+4
| | | | | | | | | | | We only want to enable ARB_transform_feedback2 if we can write to registers from batchbuffers. In order to test that, we need to be able to submit batches. And for batches to work, we need to program the initial pipeline state (like PIPELINE_SELECT), which is done from brw_state_init(). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
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