summaryrefslogtreecommitdiffstats
Commit message (Expand)AuthorAgeFilesLines
* intel: Add more Coffee Lake PCI IDsAnuj Phogat2018-01-111-1/+9
* Revert "Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+""Matt Turner2018-01-111-4/+8
* i965/fs: Add/use functions to convert to 3src_align1 vstride/hstrideMatt Turner2018-01-111-28/+41
* anv: Make sure state on primary is correct after CmdExecuteCommandsAlex Smith2018-01-111-0/+9
* svga: simplify failure code in emit_rss_vgpu9()Brian Paul2018-01-111-17/+12
* svga: remove unused fail parameter to EMIT_RS(), EMIT_RS_FLOAT()Brian Paul2018-01-111-57/+57
* svga: add assertion in svga_queue_rs()Brian Paul2018-01-111-0/+1
* svga: whitespace/formatting fixes in svga_state_rss.cBrian Paul2018-01-111-79/+75
* anv: Import mako templates only during execution of anv_extensionsAndres Gomez2018-01-111-5/+5
* glsl: cleanup shader_cache header guardTapani Pälli2018-01-111-3/+3
* anv: fix maxDescriptorSet* limitsSamuel Iglesias Gonsálvez2018-01-111-5/+5
* ac: add load_patch_vertices_in() to the abiTimothy Arceri2018-01-113-7/+26
* ac/nir: Sanitize location_frac for local variables.Bas Nieuwenhuizen2018-01-111-0/+1
* tgsi: include struct definitions for tgsi_build declarationsRob Herring2018-01-101-5/+1
* swr: Handle indirect indices in GSGeorge Kyriazis2018-01-101-8/+39
* amd/common: use ac_build_buffer_load() for emitting UBO loadsSamuel Pitoiset2018-01-101-14/+3
* amd/common: import get_{load,store}_intr_attribs() from RadeonSISamuel Pitoiset2018-01-103-31/+25
* dri_util: remove ALLOW_RGB10_CONFIGS option (v2)Marek Olšák2018-01-102-5/+2
* swr/rast: switch win32 jit format to COFFTim Rowley2018-01-101-2/+2
* swr/rast: don't use 32-bit gathers for elements < 32-bits in sizeTim Rowley2018-01-101-1/+60
* swr/rast: autogenerate named structs instead of literal structsTim Rowley2018-01-101-8/+15
* swr/rast: SIMD16 fetch shader jitter cleanupTim Rowley2018-01-101-720/+368
* swr/rast: shuffle header files for msvc pre-compiled header usageTim Rowley2018-01-1010-88/+143
* swr/rast: SIMD16 builder - cleanup naming (simd2 -> simd16)Tim Rowley2018-01-105-233/+239
* glsl/linker: Safely generate mask of possible locationsIan Romanick2018-01-101-4/+5
* glsl/linker: Mark no locations as invalid instead of marking all locationsIan Romanick2018-01-101-1/+1
* glsl: Don't handle visit_stop in several ::accept methodsIan Romanick2018-01-101-3/+6
* glsl: Remove unnecessary assignments to typeIan Romanick2018-01-101-4/+0
* nir: Silence unused parameter warningsIan Romanick2018-01-101-2/+2
* radv: Remove some typos.Bas Nieuwenhuizen2018-01-102-4/+4
* radv: Implement VK_EXT_discard_rectangles.Bas Nieuwenhuizen2018-01-105-6/+110
* radv: Add mapping between dynamic state mask and external enum.Bas Nieuwenhuizen2018-01-103-38/+79
* amd/common: bump the number of available user SGPRS to 32 on GFX9Samuel Pitoiset2018-01-101-1/+3
* radv: remove radv_pipeline_layout::push_constant_stages fieldSamuel Pitoiset2018-01-102-3/+0
* amd/common: do not rely on the pipeline for the push constants logicSamuel Pitoiset2018-01-103-9/+9
* radv/gfx9: calculate the number of ES VGPRs for merged shadersSamuel Pitoiset2018-01-101-3/+10
* radv/gfx9: enable LDS for GS only if the ES type is TESSamuel Pitoiset2018-01-101-1/+2
* amd/common: determine the ES type (VS or TES) for the GS on GFX9Samuel Pitoiset2018-01-102-0/+9
* i965/nir: lower TES PatchVerticesIn to a constant when a TCS is presentIago Toral Quiroga2018-01-101-4/+22
* glsl: remove Lower{TCS,TES}PatchVerticesInIago Toral Quiroga2018-01-104-31/+4
* i965: lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-101-0/+8
* i965/nir: add a helper to lower gl_PatchVerticesIn to a uniformIago Toral Quiroga2018-01-102-0/+27
* r600: don't emit tes samplers/views when tes isn't activeRoland Scheidegger2018-01-102-0/+19
* r600: increase number of UBOs to 15Roland Scheidegger2018-01-103-22/+37
* r600: use GET_BUFFER_RESINFO vtx fetch on eg instead of setting up constsRoland Scheidegger2018-01-104-58/+50
* r600: increase number of ubos by one to 14Roland Scheidegger2018-01-104-4/+9
* r600: set up constants needed for txq for buffers and cube maps with tesRoland Scheidegger2018-01-101-0/+16
* r600: don't emit reloc for ring buffer out into the blueRoland Scheidegger2018-01-102-8/+6
* r600: hack up num_render_backends on Juniper to 8Roland Scheidegger2018-01-101-2/+19
* winsys/radeon: fix up default enabled_rb_mask for r600Roland Scheidegger2018-01-101-6/+10
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-29 11:43:01 +0000