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* st/va: error handlingNayan Deshmukh2017-01-031-3/+15
* st/vdpau: error handlingNayan Deshmukh2017-01-033-15/+50
* vl/compositor: implement error handlingNayan Deshmukh2017-01-032-3/+12
* i965/vec4: enable ARB_gpu_shader_fp64 for HaswellIago Toral Quiroga2017-01-031-0/+3
* i965/vec4: adjust spilling costs for 64-bit registers.Iago Toral Quiroga2017-01-031-2/+13
* i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destinationIago Toral Quiroga2017-01-031-0/+12
* i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit accessIago Toral Quiroga2017-01-031-0/+24
* i965/vec4: support basic spilling of 64-bit registersIago Toral Quiroga2017-01-031-6/+28
* i965/vec4: run scalarize_df() after spillingIago Toral Quiroga2017-01-031-0/+18
* i965/vec4: prevent src/dst hazards during 64-bit register allocationIago Toral Quiroga2017-01-031-1/+7
* i965/vec4/scalarize_df: support more swizzles via vstride=0Iago Toral Quiroga2017-01-033-21/+51
* i965/vec4/scalarize_df: do not scalarize swizzles that we can support nativelyIago Toral Quiroga2017-01-033-25/+112
* i965/vec4: split instructions that read 64-bit interleaved attributesIago Toral Quiroga2017-01-031-2/+26
* i965/vec4: dump subnr for FIXED_GRFIago Toral Quiroga2017-01-031-1/+1
* i965/vec4/tes: consider register offsets during attribute setupIago Toral Quiroga2017-01-031-2/+2
* i965/vec4/tes: fix setup_payload() for 64bit data typesIago Toral Quiroga2017-01-031-1/+20
* i965/vec4/tes: fix input loading for 64bit data typesIago Toral Quiroga2017-01-031-17/+55
* i965/vec4/tcs: fix outputs for 64-bit dataIago Toral Quiroga2017-01-031-2/+29
* i965/vec4/tcs: fix input loading for 64-bit dataIago Toral Quiroga2017-01-031-4/+30
* i965/vec4/gs: fix input loading for 64bit dataSamuel Iglesias Gonsálvez2017-01-031-17/+34
* i965/vec4: fix store output for 64-bit typesIago Toral Quiroga2017-01-031-2/+25
* i965/vec4: fix attribute setup for doublesIago Toral Quiroga2017-01-031-7/+14
* i965/vec4: fix indentation in lower_attributes_to_hw_regs()Iago Toral Quiroga2017-01-031-8/+8
* i965/vec4: make emit_pull_constant_load support 64-bit loadsIago Toral Quiroga2017-01-032-55/+50
* i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit dataIago Toral Quiroga2017-01-031-4/+19
* i965/vec4: fix indentation in move_push_constants_to_pull_constants()Iago Toral Quiroga2017-01-031-30/+30
* i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit dataIago Toral Quiroga2017-01-031-2/+18
* i965/vec4: fix scratch writes for 64bit dataIago Toral Quiroga2017-01-031-9/+55
* i965/vec4: fix scratch reads for 64bit dataIago Toral Quiroga2017-01-031-2/+14
* i965/vec4: fix scratch offset for 64bit dataIago Toral Quiroga2017-01-031-6/+16
* i965/vec4: do not split scratch read/write opcodesIago Toral Quiroga2017-01-031-0/+9
* i965/vec4: Do not use DepCtrl with 64-bit instructionsIago Toral Quiroga2017-01-031-1/+13
* i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8 platformsIago Toral Quiroga2017-01-031-3/+6
* i965/vec4: don't copy propagate misaligned registersSamuel Iglesias Gonsálvez2017-01-031-0/+3
* i965/vec4: don't propagate single-precision uniforms into 4-wide instructionsIago Toral Quiroga2017-01-031-0/+11
* i965/vec4: Prevent copy propagation from violating pre-gen8 restrictionsIago Toral Quiroga2017-01-031-0/+7
* i965/vec4: prevent copy-propagation from values with a different type sizeIago Toral Quiroga2017-01-031-0/+7
* i965/vec4: don't constant propagate 64-bit immediatesConnor Abbott2017-01-031-0/+7
* i965/vec4: Fix SSBO stores for 64-bit dataIago Toral Quiroga2017-01-031-8/+32
* i965/vec4: Fix SSBO loads for 64-bit dataIago Toral Quiroga2017-01-031-4/+29
* i965/vec4: Fix UBO loads for 64-bit dataIago Toral Quiroga2017-01-031-15/+34
* i965/vec4: Add a shuffle_64bit_data helperIago Toral Quiroga2017-01-032-0/+76
* i965/vec4: support multiple dispatch widths and groups in the IR builder.Iago Toral Quiroga2017-01-031-2/+37
* i965/vec4: Lower 64-bit MADIago Toral Quiroga2017-01-032-0/+45
* i965/vec4/nir: do not emit 64-bit MADIago Toral Quiroga2017-01-031-5/+12
* i965/vec4: Skip swizzle to subnr in 3src instructions with DF operandsIago Toral Quiroga2017-01-031-1/+4
* i965/vec4: fix indentation in pack_uniform_registersIago Toral Quiroga2017-01-031-15/+15
* i965/vec4: fix pack_uniform_registers for doublesIago Toral Quiroga2017-01-031-2/+9
* i965/vec4: teach register coalescing about 64-bitIago Toral Quiroga2017-01-031-3/+19
* i965/disasm: fix subreg for dst in Align16 modeIago Toral Quiroga2017-01-031-1/+1
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