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* xmlconfig: add missing #includeEric Engestrom2019-06-271-0/+3
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* xmlpool: fix typo in commentEric Engestrom2019-06-271-2/+2
| | | | | | | | s/otions/options/, and while here let's give the full path to xmlpool.h since `../` won't be true in the generated file. Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* iris: Also properly restore INTERFACE_DESCRIPTOR_DATA buffer objectKenneth Graunke2019-06-272-4/+10
| | | | | We were at least cleaning up this reference, but we were failing to pin it in iris_restore_compute_saved_bos.
* iris: Fix resource tracking for CS thread ID bufferKenneth Graunke2019-06-272-2/+8
| | | | | | | | | | | | | | | | | | Today, we stream the compute shader thread IDs simply because they're (annoyingly) relative to dynamic state base address. We could upload them once at compile time, but we'd need a separate non-streaming uploader for IRIS_MEMZONE_DYNAMIC, and I'm not sure it's worth it. stream_state pins the buffer for use in the current batch, but also returns a reference to the pipe_resource. We dropped this reference on the floor, leaking a reference basically every time we dispatched a compute shader after switching to a new one. The reason it returns a reference is so that we can hold on to it and re-pin it in iris_restore_compute_saved_bos, which we were also failing to do. So if we actually filled up a batch with repeated dispatches to the same compute shader, and flushed, then continued dispatching, we would fail to pin it and likely GPU hang.
* iris: Only bother with thread ID upload if doing MEDIA_CURBE_LOADKenneth Graunke2019-06-271-13/+13
| | | | | | We were unconditionally uploading the new data, but then conditionally using it with MEDIA_CURBE_LOAD. If we're not going to emit the command, there's no point in uploading the data.
* iris: Do MEDIA_CURBE_LOAD when IRIS_DIRTY_CS is set, not constantsKenneth Graunke2019-06-271-1/+1
| | | | | | We only use push the compute shader thread IDs, not any actual constant buffer data. So we should track the compute shader variant changing, not constbuf changes.
* iris: Drop UBO range stuff from iris_restore_compute_saved_bosKenneth Graunke2019-06-271-24/+0
| | | | Compute doesn't use UBO ranges (annoyingly), so this is dead code.
* iris: Properly align interface descriptor data addressesKenneth Graunke2019-06-271-1/+1
| | | | | | | | MEDIA_INTERFACE_DESCRIPTOR's Interface Descriptor Data Start Address field's docs say: "This bit specifies the 64-byte aligned address..." And we were doing 32. Superfluous thread ID uploading was apparently saving us from GPU hangs in most cases.
* mesa: use a correct function return typeAndrii Simiklit2019-06-272-2/+2
| | | | | | | | v2: standard 'bool' can be used ( Eric Engestrom <[email protected]> ) Reviewed-by: Eric Engestrom <[email protected]> Signed-off-by: Andrii Simiklit <[email protected]>
* panfrost/decode: Mention the address of a few descriptorsTomeu Vizoso2019-06-271-13/+11
| | | | | | | | When the fault_pointer field in the header is set, we can get some idea of which descriptor the HW isn't happy with if we know their addresses. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Wait for a job to finish before dumpingTomeu Vizoso2019-06-271-2/+4
| | | | | | | | Then we can get some information back about any exception that might have happened. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Decode exception statusTomeu Vizoso2019-06-271-2/+6
| | | | | | | | Arm's kernel driver mentions how to decode this field, which makes a bit clearer what had happened. Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost/decode: Print AFBC struct when appropriateTomeu Vizoso2019-06-271-2/+1
| | | | | Signed-off-by: Tomeu Vizoso <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* radv: only export clip/cull distances if PS reads themSamuel Pitoiset2019-06-273-4/+15
| | | | | | | | | | | | | | | | The only exception is the GS copy shader which emits them unconditionally. Totals from affected shaders: SGPRS: 71320 -> 71008 (-0.44 %) VGPRS: 54372 -> 54240 (-0.24 %) Code Size: 2952628 -> 2941368 (-0.38 %) bytes Max Waves: 9689 -> 9723 (0.35 %) This helps Dota2, Doom, GTAV and Hitman 2. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: fix FMASK expand if layerCount is VK_REMAINING_ARRAY_LAYERSSamuel Pitoiset2019-06-271-1/+1
| | | | | | | | This doesn't fix anything known, but it's likely going to break if layerCount is ~0U. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* iris: Disable loop unrolling in GLSL IR.Kenneth Graunke2019-06-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leave it to NIR instead, like i965 does. Thanks to Tim Arceri for noticing that I'd left this enabled by accident. shader-db results on Skylake: total instructions in shared programs: 15522628 -> 15521642 (<.01%) instructions in affected programs: 94008 -> 93022 (-1.05%) helped: 34 HURT: 33 helped stats (abs) min: 12 max: 48 x̄: 33.82 x̃: 42 helped stats (rel) min: 0.06% max: 22.14% x̄: 9.86% x̃: 10.89% HURT stats (abs) min: 1 max: 16 x̄: 4.97 x̃: 3t HURT stats (rel) min: 0.82% max: 3.77% x̄: 1.73% x̃: 1.53% 95% mean confidence interval for instructions value: -20.08 -9.35 95% mean confidence interval for instructions %-change: -5.95% -2.36% Instructions are helped. total cycles in shared programs: 367105221 -> 367074230 (<.01%) cycles in affected programs: 10017660 -> 9986669 (-0.31%) helped: 266 HURT: 184 helped stats (abs) min: 1 max: 9556 x̄: 151.35 x̃: 12 helped stats (rel) min: 0.08% max: 59.91% x̄: 4.66% x̃: 1.67% HURT stats (abs) min: 1 max: 1716 x̄: 50.37 x̃: 6 HURT stats (rel) min: <.01% max: 24.40% x̄: 2.42% x̃: 0.85% 95% mean confidence interval for cycles value: -133.90 -3.84 95% mean confidence interval for cycles %-change: -2.44% -1.10% Cycles are helped. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* st/mesa: Set EmitNoIndirectSampler if GLSLVersion < 400.Kenneth Graunke2019-06-261-1/+1
| | | | | | | | | | | | | | | This patch changes the code which sets EmitNoIndirectSampler to check the core profile GLSL version, rather than the ARB_gpu_shader5 extension enable. st/mesa exposes ARB_gpu_shader5 if GLSLVersion (in core profiles) or GLSLVersionCompat (in compat profiles) >= 400. The Intel drivers do not currently expose ARB_gpu_shader5 in compat profiles. But the backend can absolutely handle indirect samplers. Looking at the core profile version number should be a good indication of what the driver supports. Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Timothy Arceri <[email protected]>
* iris: Delete dead ice->state.streamout_strides field.Kenneth Graunke2019-06-261-3/+0
| | | | Nothing uses this, it must be a remnant from an earlier approach.
* nir/algebraic: Add helpers and a rule involving wrappingCaio Marcelo de Oliveira Filho2019-06-262-0/+15
| | | | | | | | The helpers are needed so we can use the syntax `instr(cond)` in the algebraic rules. Add simple rule for dropping a pair of mul-div of the same value when wrapping is guaranteed to not happen. Reviewed-by: Jason Ekstrand <[email protected]>
* spirv: Implement NoSignedWrap and NoUnsignedWrap decorationsCaio Marcelo de Oliveira Filho2019-06-261-0/+33
| | | | | | | | | | | | | | | | When handling the specified ALU operations, check for the decorations and set nir_alu_instr no_signed_wrap and no_unsigned_wrap flags accordingly. v2: Add a glsl_base_type_is_unsigned_integer() helper. (Karol) v3: Rename helper to glsl_base_type_is_uint(). v4: Use two flags, so we don't need the helper anymore. (Connor) v5: Pass alu directly to handle function. (Jason) Reviewed-by: Karol Herbst <[email protected]> [v3] Reviewed-by: Jason Ekstrand <[email protected]>
* nir: Add a no wrapping bits to nir_alu_instrCaio Marcelo de Oliveira Filho2019-06-265-8/+36
| | | | | | | | | | | | | | | | | | | | | | They indicate the operation does not cause overflow or underflow. This is motivated by SPIR-V decorations NoSignedWrap and NoUnsignedWrap. Change the storage of `exact` to be a single bit, so they pack together. v2: Handle no_wrap in nir_instr_set. (Karol) v3: Use two separate flags, since the NIR SSA values and certain instructions are typeless, so just no_wrap would be insufficient to know which one was referred to. (Connor) v4: Don't use nir_instr_set to propagate the flags, unlike `exact`, consider the instructions different if the flags have different values. Fix hashing/comparing. (Jason) Reviewed-by: Karol Herbst <[email protected]> [v1] Reviewed-by: Jason Ekstrand <[email protected]>
* docs: add news item and link release notes for 19.0.8Dylan Baker2019-06-262-0/+10
| | | | This is an emergency release due to a critical bug.
* docs: Add mesa 19.0.8 sha256 sumsDylan Baker2019-06-261-1/+2
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* docs: Add docs for 19.0.8Dylan Baker2019-06-261-0/+61
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* nir: remove fnot/fxor/fand/for opcodesJonathan Marek2019-06-269-40/+4
| | | | | | | | | | There doesn't seem to be any reason to keep these opcodes around: * fnot/fxor are not used at all. * fand/for are only used in lower_alu_to_scalar, but easily replaced Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nir: opt_vectorize: combine different constant sourcesJonathan Marek2019-06-261-2/+25
| | | | | | | | We can vectorize instructions with different constant sources by creating a new load_const and using that. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Merge embedded constantsAlyssa Rosenzweig2019-06-261-19/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Midgard, a bundle consists of a few ALU instructions. Within the bundle, there is room for an optional 128-bit constant; this constant is shared across all instructions in the bundle. Unfortunately, many instructions want a 128-bit constant all to themselves (how selfish!). If we run out of space for constants in a bundle, the bundle has to be broken up, incurring a performance and space penalty. As an optimization, the scheduler now analyzes the constants coming in per-instruction and attempts to merge shared components, adjusting the swizzle accessing the bundle's constants appropriately. Concretely, given the GLSL: (a * vec4(1.5, 0.5, 0.5, 1.0)) + vec4(1.0, 2.3, 2.3, 0.5) instead of compiling to the naive two bundles: vmul.fmul [temp], [a], r26 fconstants 1.5, 0.5, 0.5, 1.0 vadd.fadd [out], [temp], r26 fconstants 1.0, 2.3, 2.3, 0.5 The scheduler can now fuse into a single (pipelined!) bundle: vmul.fmul [temp], [a], r26.xyyz vadd.fadd [out], [temp], r26.zwwy fconstants 1.5, 0.5, 1.0, 2.3 Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Share swizzle composeAlyssa Rosenzweig2019-06-262-8/+30
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Share swizzle/mask codeAlyssa Rosenzweig2019-06-262-30/+32
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Fix checksumming typoAlyssa Rosenzweig2019-06-261-1/+1
| | | | | Fixes: 3e6c6bb0 ("panfrost: Merge checksum buffer with main BO") Signed-off-by: Alyssa Rosenzweig <[email protected]>
* iris: Fix overzealous query object batch flushing.Kenneth Graunke2019-06-261-4/+4
| | | | | | | | | | | | | | | | | | | | | | In the past, each query object had their own BO. Checking if the batch referenced that BO was an easy way to check if commands were still queued to compute the query value. If so, we needed to flush. More recently (c24a574e6c), we started using an u_upload_mgr for query objects, placing multiple queries in the same BO. One side-effect is that iris_batch_references is a no longer a reasonable way to check if commands are still queued for our query. Ours might be done, but a later query that happens to be in the same BO might be queued. We don't want to flush in that case. Instead, check if the current batch's signalling syncpt is the one we referenced when ending the query. We know the syncpt can't have been reused because our query is holding a reference, so a simple pointer comparison should suffice. Removes all batch flushing caused by query objects in Shadow of Mordor. Reviewed-by: Chris Wilson <[email protected]>
* iris: Make an iris_batch_get_signal_syncpt() helper.Kenneth Graunke2019-06-261-3/+14
| | | | | | | This returns a pointer to the signalling syncpt, without incrementing the reference count. This can be useful for comparisons. Reviewed-by: Chris Wilson <[email protected]>
* panfrost: Remove unneeded check in panfrost_scissor_culls_everything()Boris Brezillon2019-06-261-1/+1
| | | | | | | | The ss local var is guaranteed to be != NULL. Get rid of this useless check. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Update copyright identifiersAlyssa Rosenzweig2019-06-2614-14/+14
| | | | | | | "Collabora, Ltd." should be listed in lieu of simply "Collabora" Signed-off-by: Alyssa Rosenzweig <[email protected]> Suggested-by: Daniel Stone <[email protected]>
* panfrost/midgard: Reorder to permit constant biasAlyssa Rosenzweig2019-06-262-67/+61
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Add helper to encode constant biasAlyssa Rosenzweig2019-06-261-0/+34
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/midgard: Handle negative immediate biasAlyssa Rosenzweig2019-06-262-4/+5
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* freedreno: correct batch_depends_on() logicRob Clark2019-06-261-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: drop unused arg from fd_batch_flush()Rob Clark2019-06-2612-23/+23
| | | | | | | The `force` arg has been unused for a while.. but apparently I forgot to garbage collect it. Signed-off-by: Rob Clark <[email protected]>
* st/glsl: fix silly regression finding gs/tes variantsTimothy Arceri2019-06-261-1/+1
| | | | | | Fixes: d19fe5e67a39 ("st/glsl: support clamping color outputs in compat for gs/tes") Reviewed-by: Ilia Mirkin <[email protected]>
* st/glsl: support clamping color outputs in compat for gs/tesTimothy Arceri2019-06-264-13/+60
| | | | | | | This support requires the driver to be a NIR driver as we use the NIR lowering pass to do the clamping. Reviewed-by: Kenneth Graunke <[email protected]>
* nir: add tess support to nir_lower_clamp_color_outputs()Timothy Arceri2019-06-261-0/+1
| | | | | | | This will be used to add compat profile support for higher GL versions. Reviewed-by: Kenneth Graunke <[email protected]>
* glsl: Fix round64 conversion functionSagar Ghuge2019-06-251-9/+12
| | | | | | | | | | | | | | | | | | | | Fix round64 function to handle round to nearest even cases specially with positive and negative numbers with fraction part 0.5. v2: 1) Simplify unused bits (Elie Tournier) Fixes: KHR-GL45.gpu_shader_fp64.builtin.round_dvec2 KHR-GL45.gpu_shader_fp64.builtin.round_dvec3 KHR-GL45.gpu_shader_fp64.builtin.round_dvec4 KHR-GL45.gpu_shader_fp64.builtin.roundeven_double KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec2 KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec3 KHR-GL45.gpu_shader_fp64.builtin.roundeven_dvec4 Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Elie Tournier <[email protected]> Acked-by: Anuj Phogat <[email protected]>
* panfrost/ci: Add RK3288 flipflops I don't want to deal with right nowAlyssa Rosenzweig2019-06-251-0/+6
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/ci: Update failures listAlyssa Rosenzweig2019-06-251-363/+3
| | | | | | | | A ton of tests were fixed by this series. A few were incorrectly passing before (QualityError, for instance) and now are explicitly failing. A few legitimate regressions but overwhelmingly positive. Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost/ci: Set MESA_GLES_VERSION_OVERRIDE=3.0Alyssa Rosenzweig2019-06-251-0/+1
| | | | | | | | Fixes cube map tests due to disagreements between Mesa, dEQP, and the spec... Signed-off-by: Alyssa Rosenzweig <[email protected]> Cc: Tomeu Vizoso <[email protected]>
* panfrost/ci: Run full set of mipmap testsAlyssa Rosenzweig2019-06-251-3/+0
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Advertise support for other 8-bit UNORM formatsAlyssa Rosenzweig2019-06-251-26/+15
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Use pipe_surface->format directly in blitterAlyssa Rosenzweig2019-06-251-1/+1
| | | | Signed-off-by: Alyssa Rosenzweig <[email protected]>
* panfrost: Invert swizzle for renderingAlyssa Rosenzweig2019-06-251-2/+30
| | | | | | Fixes rendering to e.g. alpha textures. Signed-off-by: Alyssa Rosenzweig <[email protected]>
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