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* radv: remove unused radv_meta_state::btoi::render_pass handleSamuel Pitoiset2017-10-021-1/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not check the number of levels when doing fast htileSamuel Pitoiset2017-10-021-3/+0
| | | | | | | | We shouldn't reach this point because HTILE is only enabled when the number of levels is 1. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: cleanup radv_device_finish_meta_XXX() helpersSamuel Pitoiset2017-10-028-219/+136
| | | | | | | Unnecessary to double check that handles are not NULL. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: select the pipeline outside of emit_fast_clear_flush()Samuel Pitoiset2017-10-021-12/+11
| | | | | | | It can't change during the decompression pass. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: drop useless param in emit_depth_decomp()Samuel Pitoiset2017-10-021-5/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: drop useless check in depth_view_can_fast_clear()Samuel Pitoiset2017-10-021-2/+1
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_subpass_clear_attachment() helperSamuel Pitoiset2017-10-021-20/+32
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_attachment_needs_clear() helperSamuel Pitoiset2017-10-021-39/+31
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: remove unused param in radv_handle_{cmask,dcc}_image_transition()Samuel Pitoiset2017-10-021-8/+4
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_vi_dcc_enabled() helperSamuel Pitoiset2017-10-023-2/+7
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: do not need to double zero-init the meta state structuresSamuel Pitoiset2017-10-0212-28/+0
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: inline destroy_render_pass()Samuel Pitoiset2017-10-021-9/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: use pipeline handles instead of objects for meta clear operationsSamuel Pitoiset2017-10-022-44/+36
| | | | | | | To be consistent with other meta operations. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: inline blit2d_unbind_dst()Samuel Pitoiset2017-10-021-9/+3
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rework DCC/CMASK/FMASK/HTILE allocationsSamuel Pitoiset2017-10-021-27/+56
| | | | | | | Add helpers and some comments to make the thing more readable. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* meson: fix version typo + grammarEric Engestrom2017-10-021-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Dylan Baker <[email protected]>
* i965: skip reading unused slots at the begining of the URB for the FSIago Toral Quiroga2017-10-023-14/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can start reading the URB at the first offset that contains varyings that are actually read in the URB. We still need to make sure that we read at least one varying to honor hardware requirements. This helps alleviate a problem introduced with 99df02ca26f61 for separate shader objects: without separate shader objects we assign locations sequentially, however, since that commit we have changed the method for SSO so that the VUE slot assigned depends on the number of builtin slots plus the location assigned to the varying. This fixed layout is intended to help SSO programs by avoiding on-the-fly recompiles when swapping out shaders, however, it also means that if a varying uses a large location number close to the maximum allowed by the SF/FS units (31), then the offset introduced by the number of builtin slots can push the location outside the range and trigger an assertion. This problem is affecting at least the following CTS tests for enhanced layouts: KHR-GL45.enhanced_layouts.varying_array_components KHR-GL45.enhanced_layouts.varying_array_locations KHR-GL45.enhanced_layouts.varying_components KHR-GL45.enhanced_layouts.varying_locations which use SSO and the the location layout qualifier to select such location numbers explicitly. This change helps these tests because for SSO we always have to include things such as VARYING_SLOT_CLIP_DIST{0,1} even if the fragment shader is very unlikely to read them, so by doing this we free builtin slots from the fixed VUE layout and we avoid the tests to crash in this scenario. Of course, this is not a proper fix, we'd still run into problems if someone tries to use an explicit max location and read gl_ViewportIndex, gl_LayerID or gl_CullDistancein in the FS, but that would be a much less common bug and we can probably wait to see if anyone actually runs into that situation in a real world scenario before making the decision that more aggresive changes are required to support this without reverting 99df02ca26f61. v2: - Add a debug message when we skip clip distances (Ilia) - we also need to account for this when we compute the urb setup for the fragment shader stage, so add a compiler util to compute the first slot that we need to read from the URB instead of replicating the logic in both places. v3: - Make the util more generic so it can account for all unused slots at the beginning of the URB, that will make it more useful (Ken). - Drop the debug message, it was not what Ilia was asking for. Suggested-by: Kenneth Graunke <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Normalize types for FBL, FBH, etcMatt Turner2017-09-302-15/+11
| | | | | | | | | | | | Allows the instructions to be compacted. The documentation claims that some of these only accept UD types, even though the type doesn't change the operation performed. Just normalize the types to ensure we get instruction compaction. The only functional changes are for FBL and CBIT (always use UD types) and FBH (always use the same types). Reviewed-by: Kenneth Graunke <[email protected]>
* radeonsi: don't use the template keywordMarek Olšák2017-09-301-7/+7
| | | | | | for C++ editors Reviewed-by: Brian Paul <[email protected]>
* glx: don't use the template keywordMarek Olšák2017-09-301-3/+3
| | | | | | for C++ editors Reviewed-by: Brian Paul <[email protected]>
* gallium/vl: don't use the template keywordMarek Olšák2017-09-301-14/+14
| | | | | | for C++ editors Reviewed-by: Brian Paul <[email protected]>
* egl/dri2: don't use the template keywordMarek Olšák2017-09-301-3/+3
| | | | | | for C++ editors Reviewed-by: Brian Paul <[email protected]>
* radeonsi/uvd: clean up si_video_buffer_createBenedikt Schemmer2017-09-301-30/+17
| | | | | | V2: remove code duplication and one unnessecary variable, minor whitespace fix Signed-off-by: Marek Olšák <[email protected]>
* radeonsi/uvd: fix planar formats broken since f70f6baaa3bb0f8b280ac2eaea69bbMarek Olšák2017-09-301-3/+8
| | | | | Tested-by: Benedikt Schemmer <[email protected]> Reviewed-by: Christian König <[email protected]>
* gallium: add new LOD opcodeRoland Scheidegger2017-09-305-5/+74
| | | | | | | | | | The operation performed is all the same as LODQ, but with the usual differences between dx10 and GL texture opcodes, that is separate resource and sampler indices (plus result swizzling, and setting z/w channels to zero). Reviewed-by: Jose Fonseca <[email protected]> Acked-by: Nicolai Hähnle <[email protected]>
* drirc: whitelist glthread for OutlastKamil Páral2017-09-291-0/+3
| | | | | FPS increase 10-20% in starting locations on Core i5-4570 + Radeon R9 270.
* travis: Add clover build using llvm-5.0Jan Vesely2017-09-291-0/+36
| | | | | Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* travis: Add clover build using llvm-4.0Jan Vesely2017-09-291-0/+36
| | | | | | | | llvm-4 needs gcc 4.8: http://releases.llvm.org/4.0.1/docs/ReleaseNotes.html#non-comprehensive-list-of-changes-in-this-release Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* travis: Add clover build using llvm-3.9Jan Vesely2017-09-291-0/+41
| | | | | | | | | Use r600,radeonsi instead of i915 Update binutils, new linker is required for llvm-3.9: https://www.ubuntuupdates.org/package/core/trusty/universe/updates/binutils-2.26 Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* st/va: add dst rect to avoid scale on deintLeo Liu2017-09-291-6/+6
| | | | | | | | | | | For 1080p video transcode, the height will be scaled to 1088 when deint to progressive buffer. Set dst rect to make sure no scale. Fixes: 3ad8687 "st/va: use new vl_compositor_yuv_deint_full() to deint" Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Andy Furniss <[email protected]>
* radeonsi: emit DLDEXP and DFRACEXP TGSI opcodesNicolai Hähnle2017-09-292-1/+26
| | | | | | | | | Note: this causes spurious regressions in some current piglit tests, because the tests incorrectly assume that there is no denorm support for doubles. I'm going to send out a fix for those tests as well. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: emit LDEXP opcodeNicolai Hähnle2017-09-292-1/+3
| | | | | | | | The LLVM intrinsic has existed for a long time. The current name was established in LLVM 3.9. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* st/glsl_to_tgsi: use LDEXP when availableNicolai Hähnle2017-09-291-3/+7
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallium: add LDEXP TGSI instruction and corresponding capNicolai Hähnle2017-09-2920-3/+50
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* tgsi: infer that dst[1] of DFRACEXP is an integerNicolai Hähnle2017-09-295-6/+9
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallivm: add support for TGSI instructions with two outputsNicolai Hähnle2017-09-293-1/+31
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* gallivm: add dst register index to lp_build_tgsi_context::emit_storeNicolai Hähnle2017-09-296-20/+27
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* tgsi: clarify the semantics of DFRACEXPNicolai Hähnle2017-09-294-22/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The status quo is quite the mess: 1. tgsi_exec will do a per-channel computation, and store the dst[0] result (significand) correctly for each channel. The dst[1] result (exponent) will be written to the first bit set in the writemask. So per-component calculation only works partially. 2. r600 will only do a single computation. It will replicate the exponent but not the significand. 3. The docs pretend that there's per-component calculation, but even get dst[0] and dst[1] confused. 4. Luckily, st_glsl_to_tgsi only ever emits single-component instructions, and kind-of assumes that everything is replicated, generating this for the dvec4 case: DFRACEXP TEMP[0].xy, TEMP[1].x, CONST[0][0].xyxy DFRACEXP TEMP[0].zw, TEMP[1].y, CONST[0][0].zwzw DFRACEXP TEMP[2].xy, TEMP[1].z, CONST[0][1].xyxy DFRACEXP TEMP[2].zw, TEMP[1].w, CONST[0][1].zwzw Settle on the simplest behavior, which is single-component calculation with replication, document it, and adjust tgsi_exec and r600. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* tgsi: fix the documentation of DLDEXPNicolai Hähnle2017-09-291-1/+1
| | | | | | | | | Sourcing the exponent for the zw destination pair from Z is consistent with both tgsi_exec and gallivm. In practice, st_glsl_to_tgsi always generates per-channel instructions anyway. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* tgsi: infer that DLDEXP's second source has an integer typeNicolai Hähnle2017-09-294-7/+11
| | | | | Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* glsl/lower_instruction: handle denorms and overflow in ldexp correctlyNicolai Hähnle2017-09-291-64/+107
| | | | | | | | | | | | | GLSL ES requires both, and while GLSL explicitly doesn't require correct overflow handling, it does appear to require handling input inf/denorms correctly. Fixes dEQP-GLES31.functional.shaders.builtin_functions.precision.ldexp.* Cc: [email protected] Acked-by: Matt Turner <[email protected]> Acked-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* util/queue: fix a race condition in the fence codeNicolai Hähnle2017-09-291-0/+13
| | | | | | | | | | | | | | | | A tempting alternative fix would be adding a lock/unlock pair in util_queue_fence_is_signalled. However, that wouldn't actually improve anything in the semantics of util_queue_fence_is_signalled, while making that test much more heavy-weight. So this lock/unlock pair in util_queue_fence_destroy for "flushing out" other threads that may still be in util_queue_fence_signal looks like the better fix. v2: rephrase the comment Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Gustaw Smolarczyk <[email protected]>
* r600: cleanup set_occlusion_query_stateNicolai Hähnle2017-09-293-14/+3
| | | | | | | | | | | This fixes a warning caused by the fork (note the change in the function signature): ../../../../../mesa-src/src/gallium/drivers/r600/r600_state_common.c: In function ‘r600_init_common_state_functions’: ../../../../../mesa-src/src/gallium/drivers/r600/r600_state_common.c:2974:36: warning: assignment from incompatible pointer type [-Wincompatible-pointer-types] rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state; Reviewed-by: Marek Olšák <[email protected]>
* r300: add missing case PIPE_SHADER_CAP_INT64_ATOMICSNicolai Hähnle2017-09-291-0/+1
| | | | Reviewed-by: Marek Olšák <[email protected]>
* radeonsi: fix border color translation for integer texturesNicolai Hähnle2017-09-293-29/+60
| | | | | | | | | | This fixes the extremely unlikely case that an application uses 0x80000000 or 0x3f800000 as border color for an integer texture and helps in the also, but perhaps slightly less, unlikely case that 1 is used as a border color. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: clamp border colors for upgraded depth texturesNicolai Hähnle2017-09-291-59/+60
| | | | | | | | | | | | | The hardware does this automatically for unorm formats, but we need to do it manually for unorm depth formats that have been upgraded to Z32_FLOAT. Fixes dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth and others. Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi: clamp depth comparison value only for fixed point formatsNicolai Hähnle2017-09-297-14/+55
| | | | | | | | | | | | | | | | | | | The hardware usually does this automatically. However, we upgrade depth to Z32_FLOAT to enable TC-compatible HTILE, which means the hardware no longer clamps the comparison value for us. The only way to tell in the shader whether a clamp is required seems to be to communicate an additional bit in the descriptor table. While VI has some unused bits in the resource descriptor, those bits have unfortunately all been used in gfx9. So we use an unused bit in the sampler state instead. Fixes dEQP-GLES3.functional.texture.shadow.2d.linear.equal_depth_component32f and many other tests in dEQP-GLES3.functional.texture.shadow.* Fixes: d4d9ec55c589 ("radeonsi: implement TC-compatible HTILE") Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* radeonsi/gfx9: fix geometry shaders without output verticesNicolai Hähnle2017-09-291-3/+5
| | | | | | | | | | | Not that those are super common or useful, but hey! Fun corner cases of the API... Fixes dEQP-GLES31.functional.geometry_shading.emit.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* amd/common: save an instruction in the build_cube_select sequenceNicolai Hähnle2017-09-291-5/+6
| | | | | | | Avoid a v_cndmask: the absolute value is free due to input modifiers. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
* amd/common: fix build_cube_selectNicolai Hähnle2017-09-291-3/+3
| | | | | | | | | | | | Fix the custom cube coord selection sequence to be identical to the hardware v_cubesc/tc and OpenGL spec. Affects texture sampling with user-provided derivatives. Fixes dEQP-GLES3.functional.shaders.texture_functions.texturegrad.* Cc: [email protected] Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
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