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* ac/nir: Use an array instead of hashtable for SSA defs.Bas Nieuwenhuizen2018-04-101-9/+13
| | | | | | | | | Saves about 2% of compile time for F1 2017, as well as reduce code size of an optimized libvulkan_radeon.so by about 1 KiB. This still keeps the hashtable, as we also stored blocks in there. Reviewed-by: Samuel Pitoiset <[email protected]>
* st/mesa: finalise tcs/tes/geom NIR before storing it to the cacheTimothy Arceri2018-04-101-2/+9
| | | | | | | We don't create variants of the NIR so here we finalise it before caching to avoid unnecessary processing when restoring it. Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: exit st_translate_fragment_program() earlier for NIR pathTimothy Arceri2018-04-101-6/+6
| | | | | | This avoids a bunch of scanning that is only used by the TGSI path. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: tidy up si_nir_load_sampler_desc()Timothy Arceri2018-04-101-5/+3
| | | | | | | | This makes it easier to follow the code, and also initialises dynamic_index which will be useful for adding bindless textures support. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: set uses_bindless_images for imagesTimothy Arceri2018-04-101-1/+16
| | | | | | V2: add missing intrinsics (Spotted-by: Samuel Pitoiset) Reviewed-by: Marek Olšák <[email protected]>
* nir: dont lower bindless samplersTimothy Arceri2018-04-101-1/+7
| | | | | | | We neeed to skip the var if its not a uniform here as well as checking the bindless flag since UBOs can contain bindless samplers. Reviewed-by: Marek Olšák <[email protected]>
* st/glsl_to_nir: set paramater value offset as driver location for packed ↵Timothy Arceri2018-04-103-11/+11
| | | | | | | | | uniforms This allows us to simplify the code and will also be useful for supporting bindless textures. Reviewed-by: Marek Olšák <[email protected]>
* radeonsi/nir: don't add bindless samplers/images to declared bitmasksTimothy Arceri2018-04-101-6/+6
| | | | Reviewed-by: Marek Olšák <[email protected]>
* st/mesa: stop calling _mesa_init_shader_object_functions()Timothy Arceri2018-04-101-1/+0
| | | | | | | This sets the LinkShader function for the driver, but for the st we set it properly with the following call to st_init_program_functions(). Reviewed-by: Marek Olšák <[email protected]>
* anv/pipeline: Lower more constant initializers earlierJason Ekstrand2018-04-091-7/+5
| | | | | | | | Once we've gotten rid of everything but the main entrypoint, there's no reason why we should go ahead and lower them all. This is what radv does and it will make future work easier. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* spirv: Use the LOCAL_GROUP_SIZE system valueJason Ekstrand2018-04-091-15/+2
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* nir/lower_system_values: Support SYSTEM_VALUE_LOCAL_GROUP_SIZEJason Ekstrand2018-04-091-0/+10
| | | | Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* intel: aubinator: print out addresses of invalid instructionsLionel Landwerlin2018-04-101-9/+14
| | | | | Signed-off-by: Lionel Landwerlin <[email protected]> Reviewed-by: Scott D Phillips <[email protected]>
* radv: Always reset draw user SGPRs after secondary command buffer.Bas Nieuwenhuizen2018-04-091-14/+3
| | | | | | | | As we sometimes reset them to -1, -1 does not mean that they are not written by the secondary command buffer. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Reviewed-by: Samuel Pitoiset <[email protected]>
* radv: Don't set instance count using predication.Bas Nieuwenhuizen2018-04-091-1/+1
| | | | | | | | | | The packet can sometimes be skipped, but we still think the change takes effect. This just makes the packet always take effect. Fixes: ad11fc3571 "radv: don't emit unneeded vertex state." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942 Reviewed-by: Samuel Pitoiset <[email protected]>
* mesa/st/nir: fix instruction removalRob Clark2018-04-091-1/+1
| | | | | | | | | At one point this kinda worked (or at least didn't cause problems). But with deref-instructions it results in dangling deref instructions not being properly removed. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* mesa/st/nir: fix naked lowering pass callRob Clark2018-04-091-1/+1
| | | | | | | | Not using the macro means no nir_validate in debug builds, resulting in problems showing up only after later passes. Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* nir: add comment about nir_src_copy()Rob Clark2018-04-091-0/+3
| | | | | | | So it is more clear about when to use nir_instr_rewrite_src() Signed-off-by: Rob Clark <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Make the miptree clear color setter take a gl_color_unionNanley Chery2018-04-093-6/+7
| | | | | | | | We want to hide the internal details of how the miptree's clear color is calculated. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965/miptree: Move the clear color and value setter implementationsNanley Chery2018-04-092-21/+30
| | | | | | | These will get more complex in later commits. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Use the brw_context for the clear color and value settersNanley Chery2018-04-093-6/+6
| | | | | | | Do what all the other functions in the miptree API do. Reviewed-by: Topi Pohjolainen <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* radeonsi: convert dispatch packet to little endianBas Vermeulen2018-04-091-12/+12
| | | | | | | | | | | | | | | The parameters for the compute engine are wrong when using an E8860 on a big endian machine. To fix this, convert the contents of struct dispatch_packet to little endian. This ensures that get_global_id(0) and similar functions in the OpenCL code get the correct endian values, and makes my simple OpenCL program work correctly. Signed-off-by: Bas Vermeulen <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* radeonsi: correct si_vgt_param_key on big endian machinesBas Vermeulen2018-04-091-0/+13
| | | | | | | | | | | | Using mesa OpenCL failed on a big endian PowerPC machine because si_vgt_param_key is using bitfields and a 32 bit int for an index into an array. Fix si_vgt_param_key to work correctly on both little endian and big endian machines. Signed-off-by: Bas Vermeulen <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* radeonsi: don't set RB+ registers on GFX9 chips without RB+Marek Olšák2018-04-091-6/+1
| | | | | | CLEAR_STATE initializes them properly. Reviewed-by: Samuel Pitoiset <[email protected]>
* etnaviv: meson: add etnaviv_query_pm.[ch] to the sourcesEmil Velikov2018-04-091-0/+2
| | | | | | | | | | | Otherwise building the driver will fail with unresolved symbols. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105960 Fixes: 72d2043be06 ("etnaviv: add perfmon query implementation") Cc: Christian Gmeiner <[email protected]> Cc: Clayton Craft <[email protected]> Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]>
* i965: return the fourcc saved in __DRIimage when possibleXiong, James2018-04-091-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | When creating a image from a texture, the image's dri_format is set to the first plane's format, and used to look up for the fourcc. e.g. for FOURCC_NV12 texture, the dri_format is set to __DRI_IMAGE_FORMAT_R8, we end up with a wrong entry in function intel_lookup_fourcc(): { __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } }, instead of the correct one: { __DRI_IMAGE_FOURCC_NV12, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, as a result, a wrong fourcc __DRI_IMAGE_FOURCC_R8 was returned. To fix this bug, the image inherits the texture's planar_format that has the original fourcc; Upon querying, if planar_format is set, return the saved fourcc; Otherwise fall back to the old way. v3: add a bug description and "cc mesa-stable" tag (Jason) remove redundant null pointer check (Tapani) squash 2 patches into one (James) v2: fall back to intel_lookup_fourcc() when planar_format is NULL (Dongwon & Matt Roper) Cc: [email protected] Signed-off-by: Xiong, James <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* nir: Fix a typo in src/compiler/Makefile.nir.amBastien Orivel2018-04-091-1/+1
| | | | | | | | Since 31d91f019b58ca362c05db1fd0c75fedd169cd7b, the makefile tries to find the file SConstript.spirv instead of SConscript.spirv which breaks the make dist command. Reviewed-by: Brian Paul <[email protected]>
* radv: fix prefetching of vertex shader and VBOs on SISamuel Pitoiset2018-04-091-1/+1
| | | | | | | | Forgot one check... Too many mistakes for a simple change. Fixes: f1d7c16e85 ("radv: fix prefetching compute shaders on CIK and older chips") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: implement VK_AMD_shader_core_propertiesSamuel Pitoiset2018-04-092-0/+41
| | | | | | | Simple extension that only returns information for AMD hw. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add RADV_NUM_PHYSICAL_VGPRS constantSamuel Pitoiset2018-04-092-2/+6
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_get_num_physical_sgprs() helperSamuel Pitoiset2018-04-092-11/+10
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* vulkan: Update the XML and headers to 1.1.72Samuel Pitoiset2018-04-093-51/+445
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* docs: properly escape charactersAndres Gomez2018-04-091-1/+1
| | | | Signed-off-by: Andres Gomez <[email protected]>
* mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usageAndres Gomez2018-04-091-2/+8
| | | | | | | | | | Fixes: 03fd6704db9 ("mesa: Add support for a new override string MESA_GLES_VERSION_OVERRIDE") Cc: Jordan Justen <[email protected]> Cc: Ian Romanick <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API overrideMarek Olšák2018-04-092-28/+45
| | | | | | | | | | | | | | | | | | v2: - Provide a correct explanation on the envvars documentation (Ian). - Provide a more correct explanation on the function comments (Andres). v3: - Homogenize documentation and inline comments (Emil). - Correct a typo (Emil). Fixes: 2599b92eb97 ("mesa: allow forcing >=3.1 compatibility contexts with MESA_GL_VERSION_OVERRIDE") Cc: Jordan Justen <[email protected]> Cc: Ian Romanick <[email protected]> Cc: Eric Engestrom <[email protected]> Cc: Emil Velikov <[email protected]> Reviewed-by: Emil Velikov <[email protected]>
* dri_util: don't fail when not supporting ARB_compatibility with GL3.1Andres Gomez2018-04-092-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, any driver that does not support the ARB_compatibility extension will fail on GL3.1 context creation if the application does not request the forward-compatiblity flag. Restore the original check which changes mesa_api to API_OPENGL_CORE, only when: - GL3.1 is requested, without the forward-compatiblity flag. - driver does not support ARB_compatibility - as deduced by max_gl_compat_version. Fixes: a0c8b49284e ("mesa: enable OpenGL 3.1 with ARB_compatibility") v2: - Improve commit log (Emil). - Provide a correct explanation on the features documentation (Ian). Cc: Marek Olšák <[email protected]> Cc: Ian Romanick <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Eric Engestrom <[email protected]> Cc: Emil Velikov <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* dri_util: when overriding, always reset the core versionAndres Gomez2018-04-091-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | This way we won't fail when validating just because we may have a non overriden core version that is lower than the requested one, even when the compat version is high enough. For example, running glcts from VK-GL-CTS with i965, this will succeed: $ MESA_GL_VERSION_OVERRIDE=4.6 ./glcts --deqp-case=KHR-GL46.info.vendor While, this will fail: $ MESA_GL_VERSION_OVERRIDE=4.6COMPAT ./glcts --deqp-case=KHR-GL46.info.vendor Fixes: 464c56d3d5c ("dri_util: Use _mesa_override_gl_version_contextless") Cc: Ian Romanick <[email protected]> Cc: Tapani Pälli <[email protected]> Cc: Marek Olšák <[email protected]> Signed-off-by: Andres Gomez <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Reviewed-by: Tapani Pälli <[email protected]>
* radv: add radv_image_is_tc_compat_htile() helperSamuel Pitoiset2018-04-095-12/+21
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_use_dcc_for_image() helperSamuel Pitoiset2018-04-091-30/+68
| | | | | | | And add some TODOs. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: rename radv_image_is_tc_compat_htile()Samuel Pitoiset2018-04-091-3/+3
| | | | | | | | | ... to radv_use_tc_compat_htile_for_image(). This function name makes more sense to me because we want to know if and only if TC-compat HTILE should be used. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: simplify a check in radv_initialise_color_surface()Samuel Pitoiset2018-04-091-1/+1
| | | | | | | | If the image has FMASK metadata, the number of samples is > 1 because radv_image_can_enable_fmask() handles that already. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: clean up radv_vi_dcc_enabled()Samuel Pitoiset2018-04-093-8/+12
| | | | | | | And rename to radv_dcc_enabled() to be consistent. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: clean up radv_htile_enabled()Samuel Pitoiset2018-04-091-6/+9
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_image_has_{cmask,fmask,dcc,htile}() helpersSamuel Pitoiset2018-04-099-36/+72
| | | | | Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_get_cmask_fast_clear_value() helperSamuel Pitoiset2018-04-091-1/+22
| | | | | | | | DCC for MSAA textures are currently unsupported but that will be used later on. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* radv: add radv_clear_{cmask,dcc} helpersSamuel Pitoiset2018-04-094-15/+29
| | | | | | | | They will help for DCC MSAA textures and if we support mipmaps in the future. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* st/nine: Do not use scratch for face registerAxel Davy2018-04-081-1/+1
| | | | | | | | | | | | Scratch registers are reused every instructions. Since vFace is reused, a new temporary register should be used. Fixes: https://github.com/iXit/Mesa-3D/issues/311 Signed-off-by: Axel Davy <[email protected]> CC: "17.3 18.0" <[email protected]>
* etnaviv: expose perfmon query groupsChristian Gmeiner2018-04-081-2/+6
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Tested-by: Chris Healy <[email protected]>
* etnaviv: add query_group_info for perfmon countersChristian Gmeiner2018-04-082-0/+50
| | | | | Signed-off-by: Christian Gmeiner <[email protected]> Tested-by: Chris Healy <[email protected]>
* etnaviv: assign group_ids to perfmon queriesChristian Gmeiner2018-04-082-1/+56
| | | | | | | Prep work for AMD_performance_monitor support. Signed-off-by: Christian Gmeiner <[email protected]> Tested-by: Chris Healy <[email protected]>
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