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* nvc0/ir: trim out barrier sync for non-compute shadersIlia Mirkin2015-07-281-0/+6
| | | | | | | It seems like they're never necessary, and actively cause harm. This fixes some of the barrier-related piglits. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: fix barrier emissionIlia Mirkin2015-07-281-0/+2
| | | | | | immediate arguments require a flag to be set for each one Signed-off-by: Ilia Mirkin <[email protected]>
* vc4: Add support for ARB_draw_elements_base_vertex.Eric Anholt2015-07-271-1/+3
| | | | | | Gallium exposes it unconditionally, so do our best to support it. It fails on the negative index cases, but those seem unlikely to be used in the wild.
* freedreno/ir3: add transform-feedback supportRob Clark2015-07-274-4/+230
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: track "keeps" in irRob Clark2015-07-274-23/+17
| | | | | | | | | | | | Previously we had a fixed array to track kills, since they don't generate an SSA value, and then cheated by stuffing them in the outputs array before sending things through depth/sched/etc. But store instructions will need similar treatment. So convert this over to a more general array of instructions that must be kept and fix up the places that were previously relying on kills being in the output array. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add support for store instructionsRob Clark2015-07-273-6/+43
| | | | | | | | | | For store instructions, the "dst" register is a read register, not a written register. (Ie. it is the address to store to.) Lets not confuse register allocation, scheduling, etc, with these details. Instead just leave a dummy instr->regs[0], and take "dst" from instr->regs[1] and srcs following. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cleanup driver-param stuffRob Clark2015-07-273-10/+31
| | | | | | | | | Add 'enum ir3_driver_param' to track driver-param slots, and a create_driver_param() helper to avoid having the knowledge about where driver params are placed in const regs spread throughout the code as we add additional driver-params. Signed-off-by: Rob Clark <[email protected]>
* freedreno: add transform-feedback stateRob Clark2015-07-274-3/+95
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno: add resource tracking support for written buffersRob Clark2015-07-274-12/+17
| | | | | | | | With stream-out (transform-feedback) we have the case where resources are *written* by the gpu, which needs basically the same tracking to figure out when rendering must be flushed. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a3xx+a4xx: add support for vtxcnt semanticRob Clark2015-07-274-14/+31
| | | | | | This will be used for stream-out (transform-feedback) Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add stream-output support to cmdline compilerRob Clark2015-07-271-4/+22
| | | | | | A bit hard-coded configuration at the moment, but sufficient for now. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: drop unused create_input() argRob Clark2015-07-271-11/+8
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: move emit_const to ir3Rob Clark2015-07-2712-229/+263
| | | | | | | | | | | | | | | Details of the cmdstream packets are different between a3xx and a4xx, but the logic about the layout of const registers is the same, as that is dictated by the ir3 shader compiler. So rather than duplicating logic that is tightly coupled to ir3 between a3xx and a4xx, move this into ir3 and use per-generation callbacks for to build the cmdstream packets. This should make it easier to pass additional const regs (such as for transform feedback). And it also keeps the layout internal to ir3 in case we want to make the layout more dynamic some day. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: bit of shader API refactoringRob Clark2015-07-277-22/+25
| | | | | | | | | | | | Since for transform-feedback, we'll need more than just the TGSI tokens from the state object, just pass the entire state object to ir3_shader_create(). This also cleans things up a bit for some day in the future when we could take shader either as TGSI or directly NIR (for ex, glsl2nir or spirv2nir paths). In the same spirit, drop extra args from ir3_compile_shader_nir() (since it can anyways get what it needs from the ir3_shader_variant). Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: updated cat6 encodingRob Clark2015-07-275-113/+230
| | | | | | | Sync updated cat6 encoding from freedreno.git, needed to properly encode store instructions. Signed-off-by: Rob Clark <[email protected]>
* glsl: enable conservative depth, ssbo based on GLSL versionIlia Mirkin2015-07-271-2/+3
| | | | | | | | Add in missed version checks in the GLSL parser Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* docs: add news item and link release notes for mesa 10.6.3Emil Velikov2015-07-262-0/+7
| | | | Signed-off-by: Emil Velikov <[email protected]>
* docs: Add checksums for mesa 10.6.3 tarballsEmil Velikov2015-07-261-1/+2
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit ccef8901de421eae5dcc8affa14218d46cc06593)
* Add release notes for 10.6.3Emil Velikov2015-07-261-0/+105
| | | | | Signed-off-by: Emil Velikov <[email protected]> (cherry picked from commit ddc976368fef367e464472ebcc2ac4fd89eb9fd8)
* radeonsi: add fine derivate control (v2.1)Dave Airlie2015-07-254-7/+50
| | | | | | | | | | | | | This adds support for fine derivatives and enables ARB_derivative_control on radeonsi. (just fell out of my working out interpolation) v2: cleanup some bits, write a comment v2.1: take Michel's comment from the mailing list Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: fix GLSL textureGrad(samplerCube*) functionsMarek Olšák2015-07-253-34/+90
| | | | | | +4 piglits Reviewed-by: Michel Dänzer <[email protected]>
* st/mesa: don't ignore texture buffer state changesMarek Olšák2015-07-253-5/+7
| | | | | | | | Fixes piglit: spec@arb_texture_buffer_range@ranges-2 Cc: [email protected] Reviewed-by: Brian Paul <[email protected]>
* nvc0: fix geometry program revalidation of clipping paramsIlia Mirkin2015-07-251-1/+1
| | | | | | Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Cc: [email protected]
* radeonsi: ubo indexing support (v2)Dave Airlie2015-07-252-4/+13
| | | | | | | | | | | | This is required as part of ARB_gpu_shader5. no backend changes are required for this, or if any are, it's the same ones as for samplers. v2: use get_indirect_index (Marek) Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: add support for indirect samplers (v2)Dave Airlie2015-07-252-9/+42
| | | | | | | | | | | | This adds the frontend support, however the llvm backend produces the wrong pattern, however we can conditionalise enabling ARB_gpu_shader5 on whatever version of llvm we fix this in. v2: drop unneeded sampler_indirect checks (Marek) Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: split out interpolation input selectionDave Airlie2015-07-252-26/+38
| | | | | | | | | | | This is prep work for using it in the interpolation code later. Also add storage for the input interpolation mode so we can pick it up later. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* radeonsi: separate out load sample positionDave Airlie2015-07-251-18/+26
| | | | | | | | This is prep work for reusing this in the interpolation code later. Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* glsl: recognize ARB_shading_language_420pack to be enabled with 4.20+Ilia Mirkin2015-07-242-9/+14
| | | | | | | | | The 420pack extension enables various GLSL rules that need to be applied to any GLSL 4.20+ shader even if the extension is not explicitly enabled. Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* mesa: fix error checking for getting zero-sized texture imagesIlia Mirkin2015-07-241-9/+9
| | | | | | | | | | | | | | | | | | Commit 17f714836 (mesa: rearrange texture error checking order) moved the width/height/depth == 0 allowance before checking if the image was there. This was in part due to depth having to be == 1 for 2D images and width having to be == 1 for 1D images. Instead relax the height/depth checks to also accept 0 as valid. With this change, bin/arb_direct_state_access-get-textures starts passing again. Fixes: 17f714836 (mesa: rearrange texture error checking order) Signed-off-by: Ilia Mirkin <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: Fix typo in a commentAnuj Phogat2015-07-241-1/+1
| | | | Signed-off-by: Anuj Phogat <[email protected]>
* meta: Use _mesa_need_rgb_to_luminance_conversion() in decompress_texture_image()Anuj Phogat2015-07-241-5/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Change the signature of _mesa_need_rgb_to_luminance_conversion()Anuj Phogat2015-07-243-15/+20
| | | | | | | | | This allows us to handle cases when texImage->_BaseFormat doesn't match _mesa_format_get_base_format(texImage->Format). _BaseFormat is what we care about in this function. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Fix reading luminance texture as rgba in _mesa_meta_pbo_GetTexSubImage()Anuj Phogat2015-07-241-2/+34
| | | | | | | | | | | | | | After recent addition of pbo testing in piglit test getteximage-luminance, it fails on i965. This patch makes a sub test pass. This patch adds a clear color operation to meta pbo path, which I think is better than falling back to software path. V2: Fix color mask for GL_LUMINANCE_ALPHA Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Use _mesa_need_luminance_to_rgb_conversion() in decompress_texture_image()Anuj Phogat2015-07-241-10/+2
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Add a helper function _mesa_need_luminance_to_rgb_conversion()Anuj Phogat2015-07-242-0/+22
| | | | | | Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Use _mesa_unpack_format_to_base_format() to handle integer formatsAnuj Phogat2015-07-241-4/+2
| | | | | | | | | | Replace a call to mesa_base_tex_format() that handles only internal formats with a call to the new _mesa_unpack_format_to_base_format() function that handles allowed unpack formats and does not care for internal formats at all. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Add a helper function _mesa_unpack_format_to_base_format()Anuj Phogat2015-07-242-0/+47
| | | | | Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Set green, blue channels to zero only for formats with these componentsAnuj Phogat2015-07-241-3/+10
| | | | | | | | | This is an optimization which avoids setting pixel transfer operations when not required. _mesa_ReadPixels falls back to slower path if transfer operations are set. Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Don't do fragment color clamping in _mesa_meta_pbo_GetTexSubImageAnuj Phogat2015-07-241-0/+5
| | | | | | | | | | | | | | | _mesa_meta_pbo_GetTexSubImage() uses _mesa_meta_BlitFrameBuffer(), which will do fragment clamping if enabled. But fragment clamping doesn't affect ReadPixels and GetTexImage. Without this patch, piglit test arb_color_buffer_float-clear fails, when forced to use the meta pbo path. v2: Apply this fix to both glReadPixels and glGetTexImage. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* meta: Abort meta pbo path if readpixels need signed-unsigned conversionAnuj Phogat2015-07-241-0/+26
| | | | | | | | | | | | | | | | Meta pbo path for ReadPixels rely on BlitFramebuffer which doesn't support signed to unsigned integer conversions and vice versa. Without this patch, piglit test fbo_integer_readpixels_sint_uint fails, when forced to use the meta pbo path. v2: Make need_signed_unsigned_int_conversion() a static function. (Iago) Bump up the comment and the commit message. (Jason) Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Iago Toral <[email protected]>
* meta: Fix transfer operations check in meta pbo path for readpixelsAnuj Phogat2015-07-241-4/+9
| | | | | | | | | | | | | | | | | | | Currently used ctx->_ImageTransferState check is not sufficient because it doesn't include the read color clamping enabled with GL_CLAMP_READ_COLOR. So, use the helper function _mesa_get_readpixels_transfer_ops(). Also, transfer operations don't affect glGetTexImage(). So, do the check only for glReadPixles. Without this patch, arb_color_buffer_float-readpixels test fails, when forced to use meta pbo path. V2: Add a comment and bump up the commit message. Signed-off-by: Anuj Phogat <[email protected]> Cc: <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* mesa: Turn get_readpixels_transfer_ops() in to a global functionAnuj Phogat2015-07-242-7/+15
| | | | | | | | This utility function is utilized in a later patch. Cc: <[email protected]> Signed-off-by: Anuj Phogat <[email protected]> Reviewed-by: Iago Toral Quiroga <[email protected]>
* i965: Use updated kernel interface for accurate TIMESTAMP readsChris Wilson2015-07-243-17/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | I was mistaken, I thought we already had fixed this in the kernel a couple of years ago. We had not, and the broken read (the hardware shifts the register output on 64bit kernels, but not on 32bit kernels) is now enshrined into the ABI. I also had the buggy architecture reversed, believing it to be 32bit that had the shifted results. On the basis of those mistakes, I wrote commit c8d3ebaffc0d7d915c1c19d54dba61fd1e57b338 Author: Chris Wilson <[email protected]> Date: Wed Apr 29 13:32:38 2015 +0100 i965: Query whether we have kernel support for the TIMESTAMP register once Now that we do have an extended register read interface for always reporting the full 36bit TIMESTAMP (irrespective of whether the hardware is buggy or not), make use of it and in the process fix my reversed detection of the buggy reads for unpatched kernels. Signed-off-by: Chris Wilson <[email protected]> Cc: Martin Peres <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Michał Winiarski <[email protected]> Cc: Daniel Vetter <[email protected]> Tested-and-acked-by: Chris Forbes <[email protected]> Reviewed-by: Daniel Vetter <[email protected]>
* glsl/glcpp: fix SIGSEGV when checking error condition for macro redefinitionSamuel Iglesias Gonsalvez2015-07-241-2/+2
| | | | | | | | | | | | | | | Commit a6e9cd14c does not take into account than node_{a,b}->next could be NULL in some circumstances, such as in a shader containing this code: #define A 1 /* comment */ #define A 1 /* comment */ This patch fixes the segmentation fault for cases like that. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91290 Signed-off-by: Samuel Iglesias Gonsalvez <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Cc: [email protected]
* nvc0/ir: per-patch vars are in a separate address spaceIlia Mirkin2015-07-242-11/+9
| | | | | | | | | | | | | There's no need to attempt to avoid overlapping generic i/o with patch i/o. By the same token, we can't merge patch and non-patch loads/stores. This fixes at least the tes-both-input-array-*-index-rd tessellation variable-indexing tests. Signed-off-by: Ilia Mirkin <[email protected]>
* nvc0/ir: kepler can't do indirect shader input/output loads directlyIlia Mirkin2015-07-238-6/+75
| | | | | | | | | | | | | | There's a special AL2P instruction (called AFETCH in nv50 ir) which computes a "physical" value to be used with indirect addressing with ALD. Fixes tcs-input-array-*-index-rd tcs-output-array-*-index-wr varying-indexing tessellation tests on Kepler. Signed-off-by: Ilia Mirkin <[email protected]>
* radeon: Silence GCC unused-but-set-variable warnings.Vinson Lee2015-07-231-1/+5
| | | | | | | | | | | | | | | | | | | | | | radeon_fbo.c: In function 'radeon_map_renderbuffer_s8z24': radeon_fbo.c:162:9: warning: variable 'ret' set but not used [-Wunused-but-set-variable] int ret; ^ radeon_fbo.c: In function 'radeon_map_renderbuffer_z16': radeon_fbo.c:200:9: warning: variable 'ret' set but not used [-Wunused-but-set-variable] int ret; ^ radeon_fbo.c: In function 'radeon_map_renderbuffer': radeon_fbo.c:242:8: warning: variable 'ret' set but not used [-Wunused-but-set-variable] int ret; ^ radeon_fbo.c: In function 'radeon_unmap_renderbuffer': radeon_fbo.c:419:14: warning: variable 'ok' set but not used [-Wunused-but-set-variable] GLboolean ok; ^ Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* doxygen: Link GLvector4f struct members properly, avoiding invalid XML/HTML ↵Rhys Kidd2015-07-231-1/+1
| | | | | | | | warning Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* doxygen: Correct grammatical typo in math/m_vector.hRhys Kidd2015-07-231-1/+1
| | | | | | Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* mesa: minor clean-ups in shaderapi.cBrian Paul2015-07-231-7/+10
| | | | 80-column wrapping. Move break statements. Indentation fixes.
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