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* glsl: Fix ir validation for bit logic opsChad Versace2010-10-151-5/+9
| | | | | | | | | | | | In ir_validate::visit_leave(), the cases for - ir_binop_bit_and - ir_binop_bit_xor - ir_binop_bit_or were incorrect. It was incorrectly asserted that both operands must be the same type, when in fact one may be scalar and the other a vector. It was also incorrectly asserted that the resultant type was the type of the left operand, which in fact does not hold when the left operand is a scalar and the right operand is a vector.
* glsl: Implement constant expr evaluation for bitwise logic opsChad Versace2010-10-151-0/+54
| | | | | | | | Implement by adding the following cases to ir_exporession::constant_expression_value(): - ir_binop_bit_and - ir_binop_bit_or - ir_binop_bit_xor
* glsl: Implement constant expr evaluation for bit-shift opsChad Versace2010-10-151-0/+48
| | | | | | | Implement by adding the following cases to ir_expression::constant_expression_value(): - ir_binop_lshfit - ir_binop_rshfit
* glsl: Implement constant expr evaluation for bitwise-notChad Versace2010-10-151-0/+15
| | | | | Implement by adding a case to ir_expression::constant_expression_value() for ir_unop_bit_not.
* glsl: Implement ast-to-hir for binary shifts in GLSL 1.30Chad Versace2010-10-152-3/+71
| | | | | | | | | | Implement by adding the following cases to ast_expression::hir(): - ast_lshift - ast_rshift Also, implement ir validation for the new operators by adding the following cases to ir_validate::visit_leave(): - ir_binop_lshift - ir_binop_rshift
* glsl: Change generated file glsl_lexer.cppChad Versace2010-10-151-205/+215
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* glsl: Add lexer rules for << and >> in GLSL 1.30Chad Versace2010-10-151-0/+2
| | | | Commit for generated file glsl_lexer.cpp follows this commit.
* r600g: evergreen interpolation support.Dave Airlie2010-10-153-22/+149
| | | | | | | | | | | | | | On evergreen, interpolation has moved into the fragment shader, with the interpolation parmaters being passed via GPRs and LDS entries. This works out the number of interps required and reserves GPR/LDS storage for them, it also correctly routes face/position values which aren't interpolated from the vertex shader. Also if we noticed nothing is to be interpolated we always setup perspective interpolation for one value otherwise the GPU appears to lockup. This fixes about 15 piglit tests on evergreen.
* tgsi: add scanner support for centroid inputsDave Airlie2010-10-152-0/+2
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* glsl: Slightly change the semantic of _LinkedShadersIan Romanick2010-10-1410-72/+129
| | | | | | | | | | | | | | | Previously _LinkedShaders was a compact array of the linked shaders for each shader stage. Now it is arranged such that each slot, indexed by the MESA_SHADER_* defines, refers to a specific shader stage. As a result, some slots will be NULL. This makes things a little more complex in the linker, but it simplifies things in other places. As a side effect _NumLinkedShaders is removed. NOTE: This may be a candidate for the 7.9 branch. If there are other patches that get backported to 7.9 that use _LinkedShader, this patch should be cherry picked also.
* i965: Fix texturing on pre-gen5.Eric Anholt2010-10-141-5/+5
| | | | | I broke it in 06fd639c519214b6ebcbf29127b6d9ed429f8641 by only testing 2 generations of hardware :(
* llvmpipe: code to dump bytecode to file (disabled)Brian Paul2010-10-141-0/+6
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* gallivm: add compile-time option to emit inst addrs and/or line numbersBrian Paul2010-10-141-3/+10
| | | | Disabling address printing is helpful for diffing.
* mesa: remove post-convolution width/height varsBrian Paul2010-10-141-35/+19
| | | | These were left-over bits from when convolution was removed.
* glsl: Refresh autogenerated file builtin_function.cpp.Kenneth Graunke2010-10-141-0/+120
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* glsl: Add support for the 1.30 round() built-in.Kenneth Graunke2010-10-143-0/+31
| | | | | | | This implements round() via the ir_unop_round_even opcode, rather than adding a new opcode. We may wish to add one in the future, since it might enable a small performance increase on some hardware, but for now, this should suffice.
* i965: Add support for ir_unop_round_even via the RNDE instruction.Kenneth Graunke2010-10-143-0/+8
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* glsl: Add front-end support for GLSL 1.30's roundEven built-in.Kenneth Graunke2010-10-143-0/+31
| | | | Implemented using the op-code introduced in the previous commit.
* glsl: Add a new ir_unop_round_even opcode for GLSL 1.30's roundEven.Kenneth Graunke2010-10-143-0/+4
| | | | Also, update ir_to_mesa's "1.30 is unsupported" case to "handle" it.
* r300g: clean up warning due to unknown cap.Dave Airlie2010-10-151-0/+1
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* r600g: handle absolute modifier in shader translatorKeith Whitwell2010-10-151-5/+4
| | | | | | | This was being classed as unsupported in one place but used in others. Enabling it seems to work fine. Signed-off-by: Dave Airlie <[email protected]>
* r600g: emit hardware linewidthKeith Whitwell2010-10-151-1/+4
| | | | | | | Tested with demos/pixeltest - line rasterization doesn't seem to be set up for GL conventions yet, but at least width is respected now. Signed-off-by: Dave Airlie <[email protected]>
* r600/drm: fix segfaults in winsys create failure pathKeith Whitwell2010-10-151-3/+9
| | | | | | | Would try to destroy radeon->cman, radeon->kman both which were still NULL. Signed-off-by: Dave Airlie <[email protected]>
* i965: Clean up a warning in the old fragment backend.Kenneth Graunke2010-10-141-1/+5
| | | | Hopefully this code can just go away soon.
* i965: Enable the new FS backend on pre-gen6 as well.Eric Anholt2010-10-141-12/+1
| | | | | | | | | | | It is now to the point where we have no regressing piglit tests. It also fixes Yo Frankie! and Humus DynamicBranching, probably due to the piglit bias tests that work that didn't on the Mesa IR backend. As a downside, performance takes about a 5-10% performance hit at the moment (e.g. nexuiz 19.8fps -> 18.8fps), which I plan to resolve by reintroducing 16-wide fragment shaders where possible. It is a win, though, for fragment shaders using flow control.
* i965: Correctly emit the RNDZ instruction.Kenneth Graunke2010-10-142-3/+31
| | | | | | | | | | | | | | Simply using RNDU, RNDZ, or RNDE does not produce the desired result. Rather, the RND* instructions place a value in the destination register that may be 1 less than the correct answer. They can also set per-channel "increment bits" in a flag register, which, if set, mean dest needs to be incremented by 1. A second instruction - a predicated add - completes the job. Notably, RNDD always produces the correct answer in a single instruction. Fixes piglit test glsl-fs-trunc.
* i965: Use RNDZ for ir_unop_trunc in the new FS.Kenneth Graunke2010-10-141-1/+1
| | | | The existing code used RNDD, which rounds down, rather than toward zero.
* glsl: Refresh autogenerated file builtin_function.cpp.Kenneth Graunke2010-10-141-0/+60
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* glsl: Add front-end support for the "trunc" built-in.Kenneth Graunke2010-10-143-0/+31
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* i965: Use logical-not when emitting ir_unop_ceil.Kenneth Graunke2010-10-141-1/+1
| | | | Fixes piglit test glsl-fs-ceil.
* i965: Add peepholing of conditional mod generation from expressions.Eric Anholt2010-10-141-0/+88
| | | | | | | | | | This cuts usually 2 out of 3 instructions for flag reg generation (if statements, conditional assignment) by producing the conditional mod in the expression representing the boolean value. Fixes glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined (register allocation no longer fails for the conditional generation proliferation)
* i965: Add a function for handling the move of boolean values to flag regs.Eric Anholt2010-10-142-8/+19
| | | | | | This will be a place to peephole comparisions directly to the flag regs, and for now avoids using MOV with conditional mod on gen6, which is now illegal.
* Only install vtxfmt tables for OpenGLKristian Høgsberg2010-10-141-2/+4
| | | | | | GLES1 and GLES2 install their own exec pointers and don't need the Save table. Also, the SET_* macros use different indices for the different APIs so the offsets used in vtxfmt.c are actually wrong for the ES APIs.
* i965: Add a pass to the FS to split virtual GRFs to float channels.Eric Anholt2010-10-142-2/+116
| | | | Improves nexuiz performance 0.91% (+/- 0.54%, n=8)
* i965: Update the live interval when coalescing regs.Eric Anholt2010-10-141-0/+4
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* i965: Set class_sizes[] for the aligned reg pair class.Eric Anholt2010-10-141-0/+1
| | | | So far, I've only seen this be a valgrind warning and not a real failure.
* llvmpipe: don't try to emit non-existent color outputsKeith Whitwell2010-10-141-8/+9
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* Drop the "neutral" tnl moduleKristian Høgsberg2010-10-145-120/+9
| | | | | | | Just always check for FLUSH_UPDATE_CURRENT and call Driver.BeginVertices when necessary. By using the unlikely() macros, this ends up as a 10% performance improvement (for isosurf, anyway) over the old, complicated function pointer swapping.
* st/egl: Do not finish a fence that is NULL.Chia-I Wu2010-10-141-2/+4
| | | | i915g would dereference the NULL pointer.
* st/egl: Access _EGLConfig directly.Chia-I Wu2010-10-141-31/+26
| | | | | Drop the use of SET_CONFIG_ATTRIB. Fix the value of EGL_SAMPLE_BUFFERS along the way.
* egl: Access config attributes directly.Chia-I Wu2010-10-143-143/+76
| | | | Replace SET_CONFIG_ATTRIB/GET_CONFIG_ATTRIB by direct dereferences.
* egl: Use attribute names as the _EGLConfig member names.Chia-I Wu2010-10-142-69/+97
| | | | | This makes _EGLConfig more accessible and scales better when new attributes are added.
* r600g: select linear interpolate if tgsi input requests itDave Airlie2010-10-141-0/+3
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* r600g: fixup typo in macro nameDave Airlie2010-10-141-1/+1
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* r600g: fixup pos/face ena/address properlyDave Airlie2010-10-141-8/+17
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* r600g: only pick centroid coordinate when asked.Dave Airlie2010-10-142-1/+4
| | | | TGSI tells us when to use this, its not hooked up from GLSL to MESA to TGSI yet though.
* Revert "i965: fallback lineloop on sandybridge for now"Zhenyu Wang2010-10-141-7/+0
| | | | This reverts commit 73dab75b4165f7d2214a68d4ba8e3cb7aab9b4ac.
* i965: Fix GS hang on SandybridgeZhenyu Wang2010-10-144-14/+46
| | | | | | Don't use r0 for FF_SYNC dest reg on Sandybridge, which would smash FFID field in GS payload, that cause later URB write fail. Also not use r0 in any URB write requiring allocate.
* i965: Add support for rescaling GL_TEXTURE_RECTANGLE coords to new FS.Eric Anholt2010-10-131-5/+40
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* r600g: Fix texture sampling with swizzled coordsFredrik Höglund2010-10-141-1/+1
| | | | Signed-off-by: Dave Airlie <[email protected]>
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