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* r600g/llvm: Factorize code loading from const buffer.Vincent Lejeune2013-05-201-27/+24
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* i965: Add cases for ir_triop_vector_insert that assert.Kenneth Graunke2013-05-202-0/+5
| | | | | | | | | | brw_link_shader() unconditionally calls lower_vector_insert() with true as the second parameter. This means that both constant and variable indexed expressions will get lowered, so we should never see this in the backend. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Add cases for ir_binop_vector_extract that assert.Kenneth Graunke2013-05-202-0/+5
| | | | | | | | | | | | | | | do_vec_index_to_swizzle() should remove any vector extract operations with a constant index. It's unconditionally called from do_common_optimization(). do_vec_index_to_cond_assign() should remove the rest, and it is unconditionally called from brw_link_shader(). This means that we should never see ir_binop_vector_extract in the backend. Silences compiler warnings. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* llvmpipe: enable z32s8x24 formatRoland Scheidegger2013-05-181-6/+0
| | | | | | | | Now that we can handle it both for sampling and as depth/stencil enable it. Passes nearly all additional piglit tests which are now performed, with two exceptions (one being a framebuffer blit which fails for all other formats including stencil too as we don't support stencil blits, the other reporting a unexpected GL error so doesn't look to be llvmpipe's fault).
* llvmpipe: handle z32s8x24 depth/stencil formatRoland Scheidegger2013-05-189-148/+259
| | | | | | | We need to split up the depth and stencil values in this case, and there's some new logic required to handle float depth and stencil simultaneously. Also make sure we get the 64bit zs clear values and masks propagated correctly.
* llvmpipe: get rid of unused tiled/linear logicRoland Scheidegger2013-05-187-713/+50
| | | | | | | | | We do rendering to linear color buffers for quite some time, and since switching to linear depth buffers all the tiled/linear logic was unused. So get rid of (most) of it - there's still some LAYOUT_NONE things and late allocation of resources which probably could be simplified. Reviewed-by: Jose Fonseca <[email protected]>
* llvmpipe: fix bogus handling of first_layer when setting up texture samplingRoland Scheidegger2013-05-182-14/+18
| | | | | | | | | | | | The code avoided first_layer parameter in the sampler interface (and needing to do another calculation at runtime) by fixing up the base texture pointer instead. Unfortunately, this didn't actually work as we have mip-first texture layout so fixing up the base ptr by a fixed amount is very wrong if there are mipmaps present. The wrong offsets caused misrendering and crashes. Fix this by just adjusting the individual mip level offsets instead. Spotted by Jose. Reviewed-by: Jose Fonseca <[email protected]>
* gallivm: handle z32s8x24 format for samplingRoland Scheidegger2013-05-181-8/+51
| | | | | | | | | | | | | | | Since we can only sample either depth or stencil but not both only load the required bits which makes things a bit easier (it requires special handling since the format doesn't fit into 32bit). The logic for deciding if depth or stencil should be sampled is a bit odd, but seems to be what other drivers and statetrackers do: if it's a format with both depth and stencil (or just with depth) then sample depth, for sampling stencil a sampler view format with only stencil is required. Also while here fix up stencil sampling for other formats as well, though this isn't supported by mesa (ARB_stencil_texturing), and while blits would use it they don't work neither since they'd also need stencil export. Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: fix weird UCMP opcode use for bool ubo loadRoland Scheidegger2013-05-181-4/+2
| | | | | | | | | | I don't know what this code was trying to do but whatever it was it couldn't have worked since negation of integer boolean inputs while not specified as outright illegal (not yet at least) won't do anything since it doesn't affect the result of comparison with zero at all. In fact it looks like the whole instruction can just be omitted. Reviewed-by: Marek Olšák <[email protected]>
* mesa: Make FinishRenderTexture just take the renderbuffer being finished.Eric Anholt2013-05-178-18/+14
| | | | | | | Now that the rb has a reference to the teximage, we didn't need anything else out of the attachment. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Track the TexImage being rendered to in the gl_renderbuffer.Eric Anholt2013-05-1712-65/+34
| | | | | | | | | We keep having to pass the attachments around with our gl_renderbuffers because that's the only way to find what the gl_renderbuffer actually refers to. This is a step toward removing that (though drivers still need the Zoffset as well). Reviewed-by: Kenneth Graunke <[email protected]>
* radeon: Remove dead radeon_wrap_texture().Eric Anholt2013-05-171-30/+0
| | | | | | I should have killed this in my previous cleanup. Reviewed-by: Kenneth Graunke <[email protected]>
* mesa: Make gl_renderbuffers backed by EGL images use FinishRenderTexture.Eric Anholt2013-05-175-19/+35
| | | | | | | | | | | | | This is the opportunity that radeon and intel drivers rely on for flushing render targets that may get reused as textures. Before EGL, that only happened for GL_TEXTURE attachments. Fixes piglits: KHR_gl_renderbuffer_image/renderbuffer-texture OES_EGL_image/renderbuffer-texture NOTE: This is a candidate for the 9.1 branch. Reviewed-by: Kenneth Graunke <[email protected]>
* gallivm: Eliminate 8.8 fixed point intermediates from AoS sampling path.José Fonseca2013-05-175-242/+186
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change was meant as a stepping stone to use PMADDUBSW SSSE3 instruction, but actually this refactoring by itself yields a 10% speedup on texture intensive shaders (e.g, Google Earth's ocean water w/o S3TC on a Ivy Bridge machine), while giving yielding exactly the same results, whereas PMADDUBSW only gave an extra 5%, at the expense of 2bits of precision in the interpolation. I belive that the speedup of this change comes from the reduced register pressure (as 8.8 fixed point intermediates take twice the space of 8bit unorm). Also, not dealing with 8.8 simplifies lp_bld_sample_aos.c code substantially -- it's no longer necessary to have code duplicated for low and high register halfs. Note about lp_build_sample_mipmap(): the path for num_quads > 1 is never executed (as it is faster on AVX to split the 256bit wide texture computation into two 128bit chunks, in order to leverage integer opcodes). This path might be useful in the future, so in order to verify this change did not break that path I had to apply this change: @@ -1662,11 +1662,11 @@ lp_build_sample_soa(struct gallivm_state *gallivm, /* * we only try 8-wide sampling with soa as it appears to * be a loss with aos with AVX (but it should work). * (It should be faster if we'd support avx2) */ - if (num_quads == 1 || !use_aos) { + if (/* num_quads == 1 || ! */ use_aos) { if (num_quads > 1) { if (mip_filter == PIPE_TEX_MIPFILTER_NONE) { LLVMValueRef index0 = lp_build_const_int32(gallivm, 0); /* and then run texfilt mesademo: LP_NATIVE_VECTOR_WIDTH=256 ./texfilt Ran whole piglit without regressions. Reviewed-by: Roland Scheidegger <[email protected]>
* gallivm: Add and use lp_build_lerp_3d.José Fonseca2013-05-173-26/+60
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* radeon/llvm: Run standard optimization passes on conpute shader modulesTom Stellard2013-05-171-0/+15
| | | | | | The SROA and function inliner passes are espically important, because they optimize away unsupported features: functions and indirect private memory access.
* intel: Don't spam "intelReadPixels: fallback to swrast" in non-PBO case.Kenneth Graunke2013-05-161-11/+10
| | | | | | | | | | | | | | | | When an application is using PBOs, we attempt to use the BLT engine to perform ReadPixels. If that fails due to some restrictions, it's useful to raise a performance warning. In the non-PBO case, we always use a CPU mapping since getting the data into client memory requires a CPU-side copy. This is a very common case, so raising a performance warning is annoying. In particular, apitrace's image dumping code hits this path, causing it to print hundreds of thousands of performance warnings via ARB_debug_output. This tends to obscure actual errors or other important messages. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* intel: Do a depth resolve before copying images between miptrees.Paul Berry2013-05-161-0/+6
| | | | | | | | | | | | | | | | | | | When intel_finalize_mipmap_tree() calls intel_miptree_copy_teximage() to reassemble a depth miptree that has been broken apart into pieces (to deal with misalignment of levels/layers within the miptree), it just copies the depth data, not the HiZ data. This is reasonable, since the alignment restrictions of HiZ are a large part of the reason why the miptree had to be broken apart in the first place. However, in order for the depth copy to be sufficient, we need to do a depth resolve first, to make sure any deferred depth writes that are in the HiZ buffer get performed. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=64662 and https://bugs.freedesktop.org/show_bug.cgi?id=64659. NOTE: This is a candidate for stable release branches. Reviewed-by: Chad Versace <[email protected]>
* r600g: fixup for MSAA texture support checkingNiels Ole Salscheider2013-05-161-1/+1
| | | | Signed-off-by: Niels Ole Salscheider <[email protected]>
* llvmpipe: Temporary workaround to prevent segfault on array textures.José Fonseca2013-05-161-0/+3
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* gallivm: Support pointers in lp_build_print_value().José Fonseca2013-05-161-0/+2
| | | | Trivial.
* ilo: emit 3DSTATE_STENCIL_BUFFER on GEN7+Chia-I Wu2013-05-162-7/+21
| | | | | | Whether HiZ is enalbed or not, separate stencil is supported and enforced on GEN7+. Now that we support separate stencil resources, we know how to emit 3DSTATE_STENCIL_BUFFER.
* ilo: add support for stencil resources on GEN7+Chia-I Wu2013-05-168-33/+545
| | | | | | For allocations, we need to support stencil-only and separate stencil resources. For mapping, we need to support software tiling and packing/unpacking for separate stencil resources.
* winsys/intel: test for and expose address swizzlingChia-I Wu2013-05-162-0/+23
| | | | | Without knowing whether addresses are swizzled or not, we cannot manipulate a tiled surface in CPU.
* st/mesa: handle texture_from_pixmap and other surface-based textures correctlyMarek Olšák2013-05-157-63/+22
| | | | | | | | | | | | | | | | | | | | | There were 2 issues with it: 1) The texture format which should be used for texturing was only set in gl_texture_image::TexFormat, which wasn't used for sampler views. 2) Textures are sometimes reallocated under some circumstances in st_finalize_texture, which is unacceptable if the texture comes from a window system. The issues are resolved as follows: 1) If surface_based is true (texture_from_pixmap, etc.), store the format in a new variable st_texture_object::surface_format. 2) Don't reallocate a surface-based texture in st_finalize_texture. Also don't use st_ChooseTextureFormat is st_context_teximage, because the format is dictated by the caller. This fixes the glx-tfp piglit test. Reviewed-by: Adam Jackson <[email protected]>
* r600g: cleanup MSAA texture support checkingMarek Olšák2013-05-157-72/+21
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: rewrite FMASK allocation, fix FMASK texturing with 2 and 4 samplesMarek Olšák2013-05-158-37/+43
| | | | | | | | | | | | This fixes and enables texturing with compressed MSAA colorbuffers on Evergreen and Cayman. For the first time, multisample textures work on Cayman. This requires the libdrm flag RADEON_SURF_FMASK. v2: require libdrm_radeon 2.4.45 Reviewed-by: Alex Deucher <[email protected]>
* i965: Fill in brw_format_for_mesa_format for some non-rendering formats.Eric Anholt2013-05-151-18/+18
| | | | | | | | | This should have no change on driver operation, but it means that when you wonder why some format isn't supported natively, you can just look at the table above, instead of wondering if maybe there's an appropriate entry in the surface formats table that is already supported. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use native RGB_FLOAT16 support when available.Eric Anholt2013-05-151-1/+1
| | | | | | | | | Previously we would expand it to RGBA_FLOAT16. This format now comes out as framebuffer incomplete, but it seems worth the memory savings if that's what people are asking for (and GL3 does list it under "texture-only" color formats) Reviewed-by: Kenneth Graunke <[email protected]>
* intel: Add support for blitting 6 byte-per-pixel formats.Eric Anholt2013-05-151-7/+14
| | | | | | | The next commit introduces what is apparently our first one, which tripped over this in glReadPixels. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the Mesa surface formats for float RGB surfaces.Eric Anholt2013-05-151-2/+2
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use the new XRGB UNORM formats.Eric Anholt2013-05-151-3/+3
| | | | | | | This is a step on the way to removing some of our code for forcing alpha to 1, but I want easy bisecting so I'll add groups of formats separately. Reviewed-by: Kenneth Graunke <[email protected]>
* draw: More defensive coding in DRAW_GET_IDX.José Fonseca2013-05-151-2/+2
| | | | Doesn't make a difference ATM, but just in case.
* draw: Fix vsplit regression when the ib can be used directly.José Fonseca2013-05-151-1/+1
| | | | | | `ib` no longer is offseted by `istart`. Trivial.
* mesa: Stop clamping stencil reference value at specification timeChris Forbes2013-05-151-9/+0
| | | | | | | | | | | | All drivers now clamp this to the appropriate range for the bound stencil buffer when emitting stencil state. NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* swrast: Use accessor for stencil reference valuesChris Forbes2013-05-151-2/+4
| | | | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* st: Use accessor for stencil reference valuesChris Forbes2013-05-151-2/+5
| | | | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* radeon: Use accessor for stencil reference valuesChris Forbes2013-05-152-2/+5
| | | | | | | | | | | V2: Drop spurious mask with 0xff. NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* nouveau: Use accessor for stencil reference valuesChris Forbes2013-05-152-2/+5
| | | | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Acked-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* intel: Use accessor for stencil reference valuesChris Forbes2013-05-153-8/+11
| | | | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: Use accessor for stencil reference values in glGetChris Forbes2013-05-152-2/+6
| | | | | | | | | NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* mesa: add accessor for effective stencil refChris Forbes2013-05-151-0/+14
| | | | | | | | | | | | | | Clamps the stencil reference value to the range representable in the currently-bound draw framebuffer's stencil attachment. V2: Add spec quote. NOTE: This is a candidate for stable branches. Signed-off-by: Chris Forbes <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* ilo: clean up transfer format conversionChia-I Wu2013-05-151-34/+48
| | | | Map the bo directly, instead of calling transfer_map().
* ilo: rework transfer mapping method choosingChia-I Wu2013-05-151-102/+133
| | | | | | Always check if a bo is busy in choose_transfer_method() since we always need to map it in either map() or unmap(). Also determine how a bo is mapped in choose_transfer_method().
* ilo: refactor transfer mappingChia-I Wu2013-05-151-27/+52
| | | | | Add tex_get_box_offset() to compute transfer offet from the pipe_box. Add tex_get_slice_stride() to compute slice stride for a transfer.
* ilo: no writeback without PIPE_TRANSFER_WRITEChia-I Wu2013-05-151-0/+5
| | | | We should not write staging data back when PIPE_TRANSFER_WRITE is not set.
* ilo: minor cleanups for transfersChia-I Wu2013-05-151-41/+41
| | | | Rename some functions and reorder some code.
* ilo: simplify ilo_texture_get_slice_offset()Chia-I Wu2013-05-154-55/+40
| | | | Always return a tile-aligned offset. Also fix for W tiling.
* draw/gs: fix extracting of the clipZack Rusin2013-05-141-2/+4
| | | | | | | | | | The indices are not consecutive when using the geometry shader, which means we were extracting non existing values. Create an array of linear indices and always use it instead of the passed indices. Found by Jose. Signed-off-by: Zack Rusin <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* docs: Mark a few things as in progress.Kenneth Graunke2013-05-141-6/+6
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