summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
* r200: add missing symlink to radeon_tex_copy.cAlex Deucher2010-01-191-0/+1
|
* r100/r200: align to pitch updates in blit interfaceMaciej Cencora2010-01-202-4/+4
|
* r200: use common glCopyTex(Sub)Image codeMaciej Cencora2010-01-197-215/+55
|
* r100: use common glCopyTex(Sub)Image codeMaciej Cencora2010-01-198-220/+60
|
* radeon/r300/r600: share common glCopyTex(Sub)Image codeMaciej Cencora2010-01-1917-260/+97
|
* r600: align to r300 changes in the blit codeMaciej Cencora2010-01-192-9/+7
| | | | Pitch here means aligned width, not aligned width * bpp.
* r300/r600: move some bo offsets checking to blit codeMaciej Cencora2010-01-194-8/+8
| | | | In preperation for texcopy code sharing.
* r600: prepare for some code sharingMaciej Cencora2010-01-193-3/+4
|
* r300: check if blitting for given format is supported earlierMaciej Cencora2010-01-191-1/+22
| | | | Prevents failing assertions at later stage.
* r300: use nearest texture filtering for accelerated blitsMaciej Cencora2010-01-191-2/+2
|
* r300: fix Y coord flipping in accelerated blitsMaciej Cencora2010-01-191-7/+6
|
* radeon: use mesa provided _mesa_tex_target_to_face functionMaciej Cencora2010-01-192-19/+3
|
* r300: prepare for texcopy code sharingMaciej Cencora2010-01-194-48/+51
|
* radeon: add blit function to vtblMaciej Cencora2010-01-191-0/+20
|
* intel: Remove dead note_fence vtbl hook.Eric Anholt2010-01-194-10/+0
|
* i965: Improve the hashing of brw_state_cache keys to include the cache_id.Eric Anholt2010-01-191-32/+54
| | | | No measurable difference on cairoperf.
* i965: Remove obsolete comment about the state atoms.Eric Anholt2010-01-191-7/+1
|
* i965: Upload as many VS constants as possible through the push constants.Eric Anholt2010-01-195-12/+84
| | | | | | | The pull constants require sending out to an overworked shared unit and waiting for a response, while push constants are nicely loaded in for us at thread dispatch time. By putting things we access in every VS invocation there, ETQW performance improved by 2.5% +/- 1.6% (n=6).
* i965: Allow for variable-sized auxdata in the state cache.Eric Anholt2010-01-1917-168/+124
| | | | | | Everything has been constant-sized until now, but constant buffer handling changes will make us want some additional variable sized array.
* intel: Use the new DRI2 flush invalidate entrypoint to signal frame done.Eric Anholt2010-01-192-20/+21
| | | | | | | | | | | | | Previously for frame throttling we would wait on the first batch after a swap before emitting another swap, because we had no hook after a swap was emitted. This meant that if an app managed to squeeze everything it for a frame had into one batch, it would lock-step with the GPU. With the swapbuffers changes, we now have the entrypoint we want. This takes the WoW intro screen from 25% GPU idle and visibly jerky to 4-5% GPU idle and rather smooth. Other apps such as OpenArena have run into this problem as well.
* Sun compilers now support some gcc __attribute__ valuesAlan Coopersmith2010-01-1910-16/+20
| | | | | | | | | | | Sun cc 5.9 and later (__SUNPRO_C >= 0x590) support __attribute__ calls for aligned, always_inline, noinline, pure, const, and malloc. This commit includes updates to files that were regenerated by gl_XML.py after adding the __SUNPRO_C checks to it Signed-off-by: Alan Coopersmith <[email protected]> Signed-off-by: Brian Paul <[email protected]>
* Check if gcc supports -fvisibility=hidden before adding to CFLAGSAlan Coopersmith2010-01-191-1/+8
| | | | Signed-off-by: Alan Coopersmith <[email protected]>
* softpipe: remove redundant assignmentsBrian Paul2010-01-191-5/+0
| | | | We initialized width/height/depth from pt->width0/height0/depth0 above.
* r100/r200/r600: fix typo in 2b1d5ea4f0250a6a7fa312ced0a7af85e909381bAlex Deucher2010-01-193-3/+3
|
* r100/r200/r600: check if blitting for given format is supported earlierAlex Deucher2010-01-193-4/+105
| | | | based on Maciej's r300 patch.
* r100/r200: add blit support for ARGB4444Alex Deucher2010-01-192-0/+12
|
* r60: Add relocs for CB_TILE/FRAGAlex Deucher2010-01-181-5/+24
| | | | as per 46dc6fd3ed5ef96cda53641a97bc68c3bc104a9f
* docs: Clarify PIPE_TEXTURE_USAGE_DYNAMIC.Corbin Simpson2010-01-181-1/+5
|
* docs: Use proper XOR symbol.Corbin Simpson2010-01-181-4/+4
|
* r100: add blit supportAlex Deucher2010-01-187-2/+623
| | | | Only enabled with KMS.
* r200: add blit supportAlex Deucher2010-01-186-0/+604
| | | | Only enabled with KMS.
* docs: Spacing in TGSI formulae.Corbin Simpson2010-01-181-0/+21
| | | | Some of those still look atrocious. :T
* docs: Grammar and refs in Rasterizer.Corbin Simpson2010-01-181-4/+3
|
* docs: Cleanup Rasterizer a bit.Corbin Simpson2010-01-182-45/+49
| | | | I'm getting better at this, I think.
* docs: Fix terms and refs.Corbin Simpson2010-01-183-3/+5
| | | | I fail at Sphinx-style ReST.
* docs: Slowly keep fleshing out more info.Corbin Simpson2010-01-182-9/+21
|
* docs: PIPE_TEXTURE_USAGE info.Corbin Simpson2010-01-181-0/+24
| | | | From IRC with Jakob.
* i965: Clean up constbuf handling by splitting reladdr/non-reladdr loads.Eric Anholt2010-01-181-46/+68
| | | | The codepaths in the function were almost entirely different.
* i965: Only set up the stack register if it's going to get used.Eric Anholt2010-01-182-6/+23
|
* i965: Fix loads of non-relative-addr constants after a reladdr load.Eric Anholt2010-01-181-1/+7
| | | | Fixes piglit vp-arl-constant-array-huge-overwritten.
* nv50: fix constant vtxattr methodsChristoph Bumiller2010-01-181-13/+13
| | | | This function was untested, sorry.
* nv50: make instanced drawing work with edge flagsChristoph Bumiller2010-01-181-45/+162
| | | | | And fix some obvious mistakes introduced in the previous instancing commit.
* nv50: cannot exit shaders on a control flow instructionChristoph Bumiller2010-01-181-1/+9
| | | | | | | Fixes lockup triggered by this ingenious shader: 1: CALL :3 2: END 3: BGNSUB ...
* nv50: fix nv50_program->immd memory leakMarcin Slusarz2010-01-181-0/+1
|
* tgsi: Fix behaviour of dimension index.Michal Krol2010-01-183-27/+29
| | | | The dimension index always addresses the second-dimension axis.
* tgsi: Allow TEMPORARY registers as indirect address into source operands.Michal Krol2010-01-183-8/+11
|
* tgsi: Add ureg_DECL_immediate_block_uint().Michal Krol2010-01-182-0/+34
| | | | | Allows declaring a contiguous block of immediates. Useful for relative indexing.
* glsl: remove __inline directiveBrian Paul2010-01-181-1/+1
| | | | It makes no difference with gcc -O3, for example.
* st/mesa: updated comments and whitespaceBrian Paul2010-01-181-1/+7
|
* st/mesa: fix memory leak in st_translate_mesa_programMarcin Slusarz2010-01-181-4/+5
| | | | Signed-off-by: Brian Paul <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 17:56:58 +0000