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* main: Change the type argument of use_shader_program() to gl_shader_stage.Paul Berry2015-03-191-12/+11
| | | | | | | This allows it to be called from a loop. Reviewed-by: Jordan Justen <[email protected]> Reviewed-by: Kristian Høgsberg <[email protected]>
* main: Clean up a strange construction in use_shader_program().Paul Berry2015-03-191-1/+1
| | | | Reviewed-by: Jordan Justen <[email protected]>
* i965/nir: Sort uniforms direct-first and use two different uniform registersJason Ekstrand2015-03-192-7/+24
| | | | | | | | | | | | | | | | | | | | | Previously, we put all the uniforms into one big array. The problem with this approach is that, as soon as there was one indirect array acces, the backend would decide that the entire large array should be pull constants. This commit splits the array in half: first direct-only uniforms and then potentially-indirect uniforms. This may not be optimal, but it does let the backend promote things to push constants. Shader-db results on HSW: total instructions in shared programs: 4114840 -> 4112172 (-0.06%) instructions in affected programs: 43316 -> 40648 (-6.16%) helped: 116 HURT: 0 v2: Set param_size[num_direct_uniforms] only if we have indirect uniforms. This caused a bug that, strangely enough, only showed up on Broadwell vertex shaders. Reviewed-by: Connor Abbott <[email protected]>
* nir/lower_io: Add a assign_locations function that sorts by [in]direct useJason Ekstrand2015-03-192-0/+75
| | | | | | | v2: Delete the set of indirectly accessed variables when we're done with it v3: Rename from _packed to _scalar Reviewed-by: Connor Abbott <[email protected]>
* nir/lower_io: Make variable location assignment a manual operationJason Ekstrand2015-03-193-12/+9
| | | | | | | | | | Previously, we just assigned variable locations in nir_lower_io. Now, we force the user to assign variable locations for us. This gives the backend a bit more control over where variables are placed. v2: Rename from _packed to _scalar Reviewed-by: Connor Abbott <[email protected]>
* nir: Use a list instead of a hash_table for inputs, outputs, and uniformsJason Ekstrand2015-03-197-45/+32
| | | | | | | | | | | | We never did a single hash table lookup in the entire NIR code base that I found so there was no real benifit to doing it that way. I suppose that for linking, we'll probably want to be able to lookup by name but we can leave building that hash table to the linker. In the mean time this was causing problems with GLSL IR -> NIR because GLSL IR doesn't guarantee us unique names of uniforms, etc. This was causing massive rendering isues in the unreal4 Sun Temple demo. Reviewed-by: Connor Abbott <[email protected]>
* gallivm: remove unused 'builder' variableBrian Paul2015-03-191-1/+0
| | | | | Reviewed-by: Roland Scheidegger <[email protected]> Reviewed-by: Jose Fonseca <[email protected]>
* mesa: use more descriptive error messages for glUniform errorsBrian Paul2015-03-191-4/+65
| | | | | | | | Different errors for type mismatches, size mismatches and matrix/ non-matrix mismatches. Use a common format of "uniformName"@location in the messags. Reviewed-by: Martin Peres <[email protected]>
* i965/fs: Print spills:fills and number of promoted constants.Matt Turner2015-03-197-13/+25
| | | | | Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Chris Forbes <[email protected]>
* i965/fs: Emit better b2f of an expression on GEN4 and GEN5Ian Romanick2015-03-192-4/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On platforms that do not natively generate 0u and ~0u for Boolean results, b2f expressions that look like f = b2f(expr cmp 0) will generate better code by pretending the expression is f = ir_triop_sel(0.0, 1.0, expr cmp 0) This is because the last instruction of "expr" can generate the condition code for the "cmp 0". This avoids having to do the "-(b & 1)" trick to generate 0u or ~0u for the Boolean result. This means code like mov(16) g16<1>F 1F mul.ge.f0(16) null g6<8,8,1>F g14<8,8,1>F (+f0) sel(16) m6<1>F g16<8,8,1>F 0F will be generated instead of mul(16) g2<1>F g12<8,8,1>F g4<8,8,1>F cmp.ge.f0(16) g2<1>D g4<8,8,1>F 0F and(16) g4<1>D g2<8,8,1>D 1D and(16) m6<1>D -g4<8,8,1>D 0x3f800000UD v2: When the comparison is either == 0.0 or != 0.0 use the knowledge that the true (or false) case already results in zero would allow better code generation by possibly avoiding a load-immediate instruction. v3: Apply the optimization even when neither comparitor is zero. Shader-db results: GM45 (0x2A42): total instructions in shared programs: 3551002 -> 3550829 (-0.00%) instructions in affected programs: 33269 -> 33096 (-0.52%) helped: 121 Iron Lake (0x0046): total instructions in shared programs: 4993327 -> 4993146 (-0.00%) instructions in affected programs: 34199 -> 34018 (-0.53%) helped: 129 No change on other platforms. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Tapani Palli <[email protected]>
* util: Optimize _mesa_roundeven with SSE 4.1.Matt Turner2015-03-181-0/+20
| | | | | | | | | | | | The SSE 4.1 ROUND instructions let us implement roundeven directly. Otherwise we assume that the rounding mode has not been modified (as we do in the rest of Mesa) and use rint(). glibc uses the ROUND instruction in rint() after a cpuid check. This patch just lets us inline it directly when we're already building for SSE 4.1. Reviewed-by: Carl Worth <[email protected]>
* util: Add a roundeven test.Matt Turner2015-03-182-1/+143
| | | | Reviewed-by: Carl Worth <[email protected]>
* mesa: Replace _mesa_round_to_even() with _mesa_roundeven().Matt Turner2015-03-187-40/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Eric's initial patch adding constant expression evaluation for ir_unop_round_even used nearbyint. The open-coded _mesa_round_to_even implementation came about without much explanation after a reviewer asked whether nearbyint depended on the application not modifying the rounding mode. Of course (as Eric commented) we rely on the application not changing the rounding mode from its default (round-to-nearest) in many other places, including the IROUND function used by _mesa_round_to_even! Worse, IROUND() is implemented using the trunc(x + 0.5) trick which fails for x = nextafterf(0.5, 0.0). Still worse, _mesa_round_to_even unexpectedly returns an int. I suspect that could cause problems when rounding large integral values not representable as an int in ir_constant_expression.cpp's ir_unop_round_even evaluation. Its use of _mesa_round_to_even is clearly broken for doubles (as noted during review). The constant expression evaluation code for the packing built-in functions also mistakenly assumed that _mesa_round_to_even returned a float, as can be seen by the cast through a signed integer type to an unsigned (since negative float -> unsigned conversions are undefined). rint() and nearbyint() implement the round-half-to-even behavior we want when the rounding mode is set to the default round-to-nearest. The only difference between them is that nearbyint() raises the inexact exception. This patch implements _mesa_roundeven{f,}, a function similar to the roundeven function added by a yet unimplemented technical specification (ISO/IEC TS 18661-1:2014), with a small difference in behavior -- we don't bother raising the inexact exception, which I don't think we care about anyway. At least recent Intel CPUs can quickly change a subset of the bits in the x87 floating-point control register, but the exception mask bits are not included. rint() does not need to change these bits, but nearbyint() does (twice: save old, set new, and restore old) in order to raise the inexact exception, which would incur some penalty. Reviewed-by: Carl Worth <[email protected]>
* i965/fs: Ignore type in cmod prop if scan_inst is CMP.Matt Turner2015-03-181-12/+13
| | | | | | | | | | total instructions in shared programs: 6263270 -> 6203091 (-0.96%) instructions in affected programs: 2606529 -> 2546350 (-2.31%) helped: 14301 GAINED: 5 LOST: 3 Revewed-by: Jason Ekstrand <[email protected]>
* i965/nir: Make our environment variable checking smarterJason Ekstrand2015-03-181-2/+22
| | | | | | | | | Before, we enabled NIR if you set INTEL_USE_NIR to anything which mean that INTEL_USE_NIR=false would actually turn on NIR. In preparation for turning NIR on by default, this commit makes it smarter by allowing the INTEL_USE_NIR variable to work as either a force-enable or a force-disable. Reviewed-by: Mark Janes <[email protected]>
* egl: don't fill client apis string forever.Dave Airlie2015-03-191-0/+1
| | | | | | | | | We never reset the string on eglTerminate, so it grows for ever on multiple eglInitialise. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Matt Turner <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* swrast: Use BITFIELD64_BIT for arrayAttribs.Jose Fonseca2015-03-181-1/+1
| | | | | | | | | As VARYING_SLOT_MAX can be bigger than 32. I'll probably stop building swrast with MSVC in the near future, but this seems a real bug regardless. Reviewed-by: Brian Paul <[email protected]>
* scons: Don't link program_lexer.l/y twice.Jose Fonseca2015-03-181-8/+3
| | | | | | | | | program/lex.yy.c and program/program_parse.tab.c is already included in the PROGRAM_FILES variable. We still need to specify the dependency relationship though. Reviewed-by: Brian Paul <[email protected]>
* gallivm: Use INFINITY directly.Jose Fonseca2015-03-181-8/+1
| | | | | | Already done below. Reviewed-by: Brian Paul <[email protected]>
* scons: Silence MSVC warnings about overflows in constant arithmetic.Jose Fonseca2015-03-181-0/+2
| | | | | | | These get triggered even when using the standard C99 INFINITY/NAN constants. Reviewed-by: Brian Paul <[email protected]>
* scons: Disable MSVC signed/unsigned mismatch warnings.José Fonseca2015-03-181-0/+1
| | | | | | | | | | | | | By default gcc ignores the issue, and as result code that mixes signed/unsigned is so widespread through the code base that it ends up being little more than noise, potentially obscuring more pertinent warnings. Maybe one day we enable the corresponding gcc warnings and cleanup, but until then, this change disables them. Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Roland Scheidegger <[email protected]>
* docs: Update progress on ARB_direct_state_access.Laura Ekstrand2015-03-181-2/+2
| | | | Acked-by: Matt Turner <[email protected]>
* dri: add _glapi_set_nop_handler(), _glapi_new_nop_table() to dri_test.cBrian Paul2015-03-181-0/+11
| | | | | | | | I wasn't aware of these _glapi_ stub functions when I committed 4bdbb588a9d385509f9168e38bfdb76952ba469c. Fixes "make check" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89662 Reviewed-by: Mark Janes <[email protected]>
* mesa: remove MSVC warning pragmasBrian Paul2015-03-181-20/+0
| | | | | | | | Removing this block of pragmas doesn't seem to increase the number of warning generated by MSVC. Other than signed/unsigned comparison warnings there's very few other warnings nowadays. Acked-by: Matt Turner <[email protected]>
* mesa: add void to format_array_format_table_init() declarationBrian Paul2015-03-181-1/+1
| | | | | | Silences an MSVC warning where it's called from call_once(). Reviewed-by: Matt Turner <[email protected]>
* mapi: move some #includes from .h file to .c filesBrian Paul2015-03-183-3/+5
| | | | | | Just include things where they're needed. Reviewed-by: Jose Fonseca <[email protected]>
* mesa: make _mesa_alloc_dispatch_table() staticBrian Paul2015-03-182-9/+5
| | | | | | Never called from outside of context.c Reviewed-by: Jose Fonseca <[email protected]>
* mesa: reimplement dispatch table no-op function handlingBrian Paul2015-03-183-67/+37
| | | | | | | | | | | | | | | | | | | | | Use the new _glapi_new_nop_table() and _glapi_set_nop_handler() to improve how we handle calling no-op GL functions. If there's a current context for the calling thread, generate a GL_INVALID_OPERATION error. This will happen if the app calls an unimplemented extension function or it calls an illegal function between glBegin/glEnd. If there's no current context, print an error to stdout if it's a debug build. The dispatch_sanity.cpp file has some previous checks removed since the _mesa_generic_nop() function no longer exists. This fixes the piglit gl-1.0-dlist-begin-end and gl-1.0-beginend-coverage tests on Windows. Reviewed-by: Jose Fonseca <[email protected]>
* mapi: add new _glapi_new_nop_table() and _glapi_set_nop_handler()Brian Paul2015-03-185-41/+108
| | | | | | | | | | | | | | | | _glapi_new_nop_table() creates a new dispatch table populated with pointers to no-op functions. _glapi_set_nop_handler() is used to register a callback function which will be called from each of the no-op functions. Now we always generate a separate no-op function for each GL entrypoint. This allows us to do proper stack clean-up for Windows __stdcall and lets us report the actual function name in error messages. Before this change, for non-Windows release builds we used a single no-op function for all entrypoints. Reviewed-by: Jose Fonseca <[email protected]>
* freedreno/ir3: fix infinite recursion in schedRob Clark2015-03-181-1/+1
| | | | | | | One more case we need to handle. One of the src instructions for the indirect could also end up being ourself. Signed-off-by: Rob Clark <[email protected]>
* freedreno: fix spellingRob Clark2015-03-181-1/+1
| | | | Signed-off-by: Rob Clark <[email protected]>
* docs/GL3: don't list nv30Marek Olšák2015-03-181-2/+2
| | | | Suggested by Ilia Mirkin.
* docs/GL3: don't list swrastMarek Olšák2015-03-181-21/+21
| | | | | | Let's face it: This driver is unlikely to get more love. Reviewed-by: Ilia Mirkin <[email protected]>
* docs/GL3: don't list r300Marek Olšák2015-03-181-28/+28
| | | | | | | r300g already supports everything it can. There's no point in listing the driver here. Reviewed-by: Ilia Mirkin <[email protected]>
* radeonsi: increase coords array size for radeon_llvm_emit_prepare_cube_coordsMarek Olšák2015-03-182-2/+2
| | | | | | | | | radeon_llvm_emit_prepare_cube_coords uses coords[4] in some cases (TXB2 etc.) Discovered by Coverity. Reported by Ilia Mirkin. Cc: 10.5 10.4 <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* configure: check if compiler supports -Werror=vla.Jonathan Gray2015-03-181-2/+14
| | | | | | | | | | | | Check if the compiler supports -Werror=vla before using it. -Wvla was introduced with GCC 4.3 and is not present in 4.2. Fixes the build on OpenBSD. v2: Fix statement order, and quote $save_CFLAGS. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89433 Signed-off-by: Jonathan Gray <[email protected]> Signed-off-by: Jose Fonseca <[email protected]>
* i965: Defer the throttle until we submit new commandsChris Wilson2015-03-182-34/+44
| | | | | | | | | | | | | | | | | | | | | | Currently, we throttle before the user begins preparing commands for the next frame when we acquire the draw/read buffers. However, construction of the command buffer can itself take significant time relative to the frame time. If we move the throttle from the buffer acquire to the command submit phase we can allow the user to improve concurrency between the CPU and GPU (i.e. reduce the amount of time we waste inside the throttle). v2: Whitespace + delay throttling until after the next submission for greater parallelism Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Chad Versace <[email protected]> Cc: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]> [v1]
* i965: Throttle to the previous frameChris Wilson2015-03-183-11/+17
| | | | | | | | | | | | | | | | | | | | | | | | | In order to facilitate the concurrency offered by triple buffering and to offset the latency induced by swapping via an external process, which may incur extra rendering itself, only throttle to the previous frame and not the last. The second issue that mostly affects swap benchmarks, but also can incur jitter in the throttling, is that the throttle bo is closer to the next SwapBuffers rather than immediately after the previous SwapBuffers. Throttling to the previous frame doubles the maximum possible latency at the benefit of improving throughput and reducing jitter. v2: Rename "first_post_swapbuffer" batches array to a plain throttle_batch[] as the pluralisation was contorting the name and not making it clear as to whether it was the first batch or first_post_swap batch. Not least of which was that not all throttle points are SwapBuffers. Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Chad Versace <[email protected]> Cc: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* i965: Throttle rendering to an fboChris Wilson2015-03-183-9/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When rendering to an fbo, even though it may be acting as a winsys frontbuffer or just generally, we never throttle. However, when rendering to an fbo, there is no natural frame boundary. Conventionally we use SwapBuffers and glFinish, but potential callers avoid often glFinish for being too heavy handed (waiting on all outstanding rendering to complete). The kernel provides a soft-throttling option for this case that waits for rendering older than 20ms to be complete (that's a little too lax to be used for swapbuffers, but is here a useful safety net). The remaining choice is then either never to throttle, throttle after every draw call, or at after intermediate user defined point such as glFlush and thus all the implied flushes. This patch opts for the latter as that is the current method used for flushing to front buffers. v2: Defer the throttling from inside the flush to the next intel_prepare_render() and switch non-fbo frontbuffer throttling over to use the same lax method. The issuing being that glFlush()/intel_prepare_read() is just as likely to be called inside a tight loop and not at "frame" boundaries. v3: Rename from need_front_throttle to need_flush_throttle to avoid any ambiguity between front buffer rendering and fbo rendering. (Chad) v4: Whitespace Signed-off-by: Chris Wilson <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Kenneth Graunke <[email protected]> Cc: Ben Widawsky <[email protected]> Cc: Kristian Høgsberg <[email protected]> Cc: Chad Versace <[email protected]> Cc: Ian Romanick <[email protected]> Reviewed-by: Chad Versace <[email protected]>
* nir/peephole_select: Allow uniform/input loads and load_constJason Ekstrand2015-03-171-0/+25
| | | | | | | | | | | | | | | | | | | Shader-db results on HSW: total instructions in shared programs: 4174156 -> 4157291 (-0.40%) instructions in affected programs: 145397 -> 128532 (-11.60%) helped: 383 HURT: 0 GAINED: 20 LOST: 22 There are two more tests lost than gained. However, comparing this with GLSL IR vs. NIR results, the overall delta is reduced from 85/44 gained/lost on current master to 71/32 with this commit. Therefore, I think it's probably a boon since we are getting "closer" to where we were before. Reviewed-by: Connor Abbott <[email protected]>
* nir/peephole_select: Copy instructions into the block before the ifJason Ekstrand2015-03-171-13/+20
| | | | | | | | | Previously we tried to do poor-man's copy propagation as we created the select instructions. Instead, this commit just moves the instructions from the blocks inside the if into the block before. Copy propagation will take care of making sure we don't have any extra mov's in there for us. Reviewed-by: Connor Abbott <[email protected]>
* nir/peephole_select: Rename are_all_move_to_phi and use a switchJason Ekstrand2015-03-171-25/+31
| | | | Reviewed-by: Connor Abbott <[email protected]>
* glx: Handle out-of-sequence swap completion events correctly. (v2)Mario Kleiner2015-03-171-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code for emitting INTEL_swap_events swap completion events needs to translate from 32-Bit sbc on the wire to 64-Bit sbc for the events and handle wraparound accordingly. It assumed that events would be sent by the server in the order their corresponding swap requests were emitted from the client, iow. sbc count should be always increasing. This was correct for DRI2. This is not always the case under the DRI3/Present backend, where the Present extension can execute presents and send out completion events in a different order than the submission order of the present requests, due to client code specifying targetMSC target vblank counts which are not strictly monotonically increasing. This confused the wraparound handling. This patch fixes the problem by handling 32-Bit wraparound in both directions. As long as successive swap completion events real 64-Bit sbc's don't differ by more than 2^30, this should be able to do the right thing. How this is supposed to work: awire->sbc contains the low 32-Bits of the true 64-Bit sbc of the current swap event, transmitted over the wire. glxDraw->lastEventSbc contains the low 32-Bits of the 64-Bit sbc of the most recently processed swap event. glxDraw->eventSbcWrap is a 64-Bit offset which tracks the upper 32-Bits of the current sbc. The final 64-Bit output sbc aevent->sbc is computed from the sum of awire->sbc and glxDraw->eventSbcWrap. Under DRI3/Present, swap completion events can be received slightly out of order due to non-monotic targetMsc specified by client code, e.g., present request submission: Submission sbc: 1 2 3 targetMsc: 10 11 9 Reception of completion events: Completion sbc: 3 1 2 The completion sequence 3, 1, 2 would confuse the old wraparound handling made for DRI2 as 1 < 3 --> Assumes a 32-Bit wraparound has happened when it hasn't. The client can queue multiple present requests, in the case of Mesa up to n requests for n-buffered rendering, e.g., n = 2-4 in the current Mesa GLX DRI3/Present implementation. In the case of direct Pixmap presents via xcb_present_pixmap() the number n is limited by the amount of memory available. We reasonably assume that the number of outstanding requests n is much less than 2 billion due to memory contraints and common sense. Therefore while the order of received sbc's can be a bit scrambled, successive 64-Bit sbc's won't deviate by much, a given sbc may be a few counts lower or higher than the previous received sbc. Therefore any large difference between the incoming awire->sbc and the last recorded glxDraw->lastEventSbc will be due to 32-Bit wraparound and we need to adapt glxDraw->eventSbcWrap accordingly to adjust the upper 32-Bits of the sbc. Two cases, correponding to the two if-statements in the patch: a) Previous sbc event was below the last 2^32 boundary, in the previous glxDraw->eventSbcWrap epoch, the new sbc event is in the next 2^32 epoch, therefore the low 32-Bit awire->sbc wrapped around to zero, or close to zero --> awire->sbc is apparently much lower than the glxDraw->lastEventSbc recorded for the previous epoch --> We need to increment glxDraw->eventSbcWrap by 2^32 to adjust the current epoch to be one higher than the previous one. --> Case a) also handles the old DRI2 behaviour. b) Previous sbc event was above closest 2^32 boundary, but now a late event from the previous 2^32 epoch arrives, with a true sbc that belongs to the previous 2^32 segment, so the awire->sbc of this late event has a high count close to 2^32, whereas glxDraw->lastEventSbc is closer to zero --> awire->sbc is much greater than glXDraw->lastEventSbc. --> We need to decrement glxDraw->eventSbcWrap by 2^32 to adjust the current epoch back to the previous lower epoch of this late completion event. We assume such a wraparound to a higher (a) epoch or lower (b) epoch has happened if awire->sbc and glxDraw->lastEventSbc differ by more than 2^30 counts, as such a difference can only happen on wraparound, or if somehow 2^30 present requests would be pending for a given drawable inside the server, which is rather unlikely. v2: Explain the reason for this patch and the new wraparound handling much more extensive in commit message, no code change wrt. initial version. Cc: "10.3 10.4 10.5" <[email protected]> Signed-off-by: Mario Kleiner <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
* r600g: constify r600_shader_tgsi_instruction lists.Emil Velikov2015-03-171-5/+5
| | | | | | | Massive list of constant data. Annotate it as such. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: kill off r600_shader_tgsi_instruction::{tgsi_opcode,is_op3}Emil Velikov2015-03-171-591/+589
| | | | | | | | Both of which are no longer used. Use designated initializer to make things obvious as people add/remove TGSI_OPCODEs. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* r600g: use the tgsi opcode from parse.FullToken.FullInstructionEmil Velikov2015-03-171-5/+8
| | | | | | | | | ... rather than the local one in inst_info->tgsi_opcode. This will allow us to simplify struct r600_shader_tgsi_instruction. Signed-off-by: Emil Velikov <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* i965/fs: Apply gl_FrontFacing ? -1 : 1 optimization only for floatsIan Romanick2015-03-171-0/+3
| | | | | | | | | | | | | | | | At the very least, unreal4/sun-temple/102.shader_test uses this pattern for a signed integer result. However, that shader did not hit the optimization in the first place because it uses !gl_FrontFacing. I changed the shader to use remove the logical-not and reverse the other operands. I verified that incorrect code is generated before this change and correct code is generated after. Fixes fs-frontfacing-ternary-1-neg-1.shader_test. No shader-db changes. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Change try_opt_frontfacing_ternary to eliminate assertsIan Romanick2015-03-171-5/+2
| | | | | | | | If we check for the case that is actually necessary, the asserts become superfluous. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965/fs: Handle CMP.nz ... 0 and AND.nz ... 1 similarly in cmod propagationIan Romanick2015-03-172-1/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Espically on platforms that do not natively generate 0u and ~0u for Boolean results, we generate a lot of sequences where a CMP is followed by an AND with 1. emit_bool_to_cond_code does this, for example. On ILK, this results in a sequence like: add(8) g3<1>F g8<8,8,1>F -g4<0,1,0>F cmp.l.f0(8) g3<1>D g3<8,8,1>F 0F and.nz.f0(8) null g3<8,8,1>D 1D (+f0) iff(8) Jump: 6 The AND.nz is obviously redundant. By propagating the cmod, we can instead generate add.l.f0(8) null g8<8,8,1>F -g4<0,1,0>F (+f0) iff(8) Jump: 6 Existing code already handles the propagation from the CMP to the ADD. Shader-db results: GM45 (0x2A42): total instructions in shared programs: 3550829 -> 3550788 (-0.00%) instructions in affected programs: 10028 -> 9987 (-0.41%) helped: 24 Iron Lake (0x0046): total instructions in shared programs: 4993146 -> 4993105 (-0.00%) instructions in affected programs: 9675 -> 9634 (-0.42%) helped: 24 Ivy Bridge (0x0166): total instructions in shared programs: 6291870 -> 6291794 (-0.00%) instructions in affected programs: 17914 -> 17838 (-0.42%) helped: 48 Haswell (0x0426): total instructions in shared programs: 5779256 -> 5779180 (-0.00%) instructions in affected programs: 16694 -> 16618 (-0.46%) helped: 48 Broadwell (0x162E): total instructions in shared programs: 6823088 -> 6823014 (-0.00%) instructions in affected programs: 15824 -> 15750 (-0.47%) helped: 46 No chage on Sandy Bridge or on any platform when NIR is used. v2: Add unit tests suggested by Matt. Remove spurious writes_flag() check on scan_inst when scan_inst is known to be BRW_OPCODE_CMP (also suggested by Matt). v3: Fix some comments and remove some explicit int() casts in fs_reg constructors in the unit tests. Both suggested by Matt. Signed-off-by: Ian Romanick <[email protected]> Reviewed-by: Matt Turner <[email protected]>
* i965: Mark paths in linear <-> tiled functions as unreachable().Matt Turner2015-03-171-0/+16
| | | | | | | | | text data bss dec hex filename 9663 0 0 9663 25bf intel_tiled_memcpy.o before 8215 0 0 8215 2017 intel_tiled_memcpy.o after Reviewed-by: Carl Worth <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-28 17:48:55 +0000