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* draw: move tgsi-related state into a tgsi sub-structBrian Paul2012-08-165-30/+35
| | | | To better organize things a bit.
* gallium: add a shader stage/type param to some draw functionsBrian Paul2012-08-165-37/+51
| | | | | To prepare for geometry shader texture support in the draw module. Note: we still only handle the vertex shader case.
* st/mesa: silence signed/unsigned comparison warningBrian Paul2012-08-161-2/+2
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* svga: move result->key expression after result != NULL checkBrian Paul2012-08-161-1/+3
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* svga: fix result==NULL logic in emit_fs_consts()Brian Paul2012-08-161-23/+25
| | | | | | | | The previous test for result != NULL was kind of bogus since we dereferenced the pointer earlier in the code. Now, check for result != NULL first, then get the result->key info. Also, remove the useless "offset +=" code at the end.
* svga: update comment (s/SVGA_NEW_VS_RESULT/SVGA_NEW_VS_PRESCALE/)Brian Paul2012-08-161-1/+1
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* svga: rename svga_hw_vs_parameters -> svga_hw_vs_constantsBrian Paul2012-08-163-6/+6
| | | | and similarly for svga_hw_fs_parameters
* st/mesa: index can be negative in the PROGRAM_CONSTANT caseNiels Ole Salscheider2012-08-161-1/+1
| | | | | | NOTE: This is a candidate for the 8.0 branch. Reviewed-by: Brian Paul <[email protected]>
* mesa: add cast to silence warning in _mesa_pack_rgba_span_from_ints()Brian Paul2012-08-161-1/+1
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* meta: remove unused variableBrian Paul2012-08-161-1/+1
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* radeonsi: Fix symbol conflicts with r600g.Michel Dänzer2012-08-1610-268/+254
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50389 Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Fix memory leaks if returning early from some state functions.Michel Dänzer2012-08-162-12/+14
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: Fix LLVM context leak.Michel Dänzer2012-08-161-0/+1
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Don't assign virtual address space for BO that already has one.Michel Dänzer2012-08-161-1/+1
| | | | | | | | We'd end up re-using the old one and throwing away the new one anyway, but only after a roundtrip to the kernel. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Create hole for waste when allocating from va_offset.Michel Dänzer2012-08-161-0/+6
| | | | | | | Otherwise, the wasted area could never be used for an allocation again. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Fix potential address space loss in radeon_bomgr_force_va().Michel Dänzer2012-08-161-6/+13
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Delete uppermost virtual address space hole if it's at the top.Michel Dänzer2012-08-161-1/+12
| | | | | Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Fix losing holes when allocating virtual address space.Michel Dänzer2012-08-161-1/+6
| | | | | | | | | If a hole exactly matches the allocated size plus alignment, we would fail to preserve the alignment as a hole. This would result in never being able to use the alignment area for an allocation again. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Merge holes when freeing virtual address space.Michel Dänzer2012-08-161-7/+38
| | | | | | | | | | Otherwise we'll likely end up with an ever increasing amount of ever smaller holes. Requires keeping the list ordered wrt offsets. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* gallium/radeon: Make va_offset 64 bits wide.Michel Dänzer2012-08-161-1/+1
| | | | | | | | | | Otherwise we'd wrap around after 32 bits. The kernel currently limits GPU virtual address space to 4GB anyway, but that will probably change sooner or later, and this would result in confusing error messages when running out of virtual address space even now. Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* llvmpipe: Silence Coverity incorrect sizeof expression defect.Vinson Lee2012-08-151-1/+1
| | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* scons: Add option to enable floating-point textures.Vinson Lee2012-08-152-0/+5
| | | | | Signed-off-by: Vinson Lee <[email protected]> Reviewed-by: José Fonseca <[email protected]>
* glx/dri2: add dri2 prime support.Dave Airlie2012-08-161-0/+13
| | | | | | | | | | This adds support for having libGL pick a different driver for prime support. DRI_PRIME env var is set to the value retrieved from the server randr provider calls, by the calling process. (generally DRI_PRIME=1 will be the right answer). Signed-off-by: Dave Airlie <[email protected]>
* radeon/llvm: Enable if-cvtVincent Lejeune2012-08-151-0/+3
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Add callbacks needed by if-cvtVincent Lejeune2012-08-152-2/+151
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Lower branch/branch_cond into predicated jumpVincent Lejeune2012-08-157-145/+278
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Add a predicated JUMP instructionVincent Lejeune2012-08-151-0/+9
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Support for predicate bitVincent Lejeune2012-08-158-13/+125
| | | | | | | Tom Stellard: - A few changes to predicate register defs Signed-off-by: Tom Stellard <[email protected]>
* r600g: Glue to handle predicate aware output from llvmVincent Lejeune2012-08-151-11/+22
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g: Fix instruction group merge when there are predicated insts.Vincent Lejeune2012-08-151-0/+18
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeon/llvm: Do not use PV/PS if PRED_SEL does not matchVincent Lejeune2012-08-151-2/+4
| | | | Signed-off-by: Tom Stellard <[email protected]>
* r600g: Add support for predicatesVincent Lejeune2012-08-154-11/+18
| | | | Signed-off-by: Tom Stellard <[email protected]>
* radeonsi: move ps sampler state into PM4 streamChristian König2012-08-151-17/+7
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: move ps sampler views into PM4 streamChristian König2012-08-151-22/+7
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: move vertex state descriptors into PM4 streamChristian König2012-08-151-27/+9
| | | | | Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeonsi: add shader data infrastructureChristian König2012-08-153-2/+40
| | | | | | | | With this we can embed data for the shaders (like resource descriptors) into the PM4 stream. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: add support to fetch temps as vectorsChristian König2012-08-151-1/+11
| | | | | | | | Necessary for texture fetches with temp regs as source on SI. Signed-off-by: Christian König <[email protected]> Reviewed-by: Tom Stellard <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
* radeon/llvm: Remove AMDGPUUtil.cppTom Stellard2012-08-158-81/+22
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* radeon/llvm: Cleanup AMDGPUUtil.cppApostolos Bartziokas2012-08-156-119/+95
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* radeon/llvm: Lower loads from USE_SGPR adddress space during DAG loweringTom Stellard2012-08-155-66/+50
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* radeon/llvm: Add live-in registers during DAG loweringTom Stellard2012-08-159-66/+82
| | | | | | Psuedo instructions emulating live-in registers have been removed and their corresponding intrinsics are now being lowered during DAG lowering.
* radeon/llvm: Lower store_output intrinsic during DAG loweringTom Stellard2012-08-153-22/+22
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* radeon/llvm: Force VTX_READ instructions to use same reg for src and dstTom Stellard2012-08-151-0/+14
| | | | | | I was seeing some GPU hangs that seemed to be cause by ALU instructions writing to the same register used as the source for VTX_READ. Adding this constraint to the VTX_READ instructions avoids this situation.
* radeonsi: fix build breakage after u_blitter changesMarek Olšák2012-08-151-3/+3
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* gallium/u_blitter: document custom meta helpersMarek Olšák2012-08-154-10/+19
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* r600g: disable handling of DISCARD_RANGEMarek Olšák2012-08-151-0/+2
| | | | https://bugs.freedesktop.org/show_bug.cgi?id=53130
* r600g: implement timestamp query and get_timestamp hookMarek Olšák2012-08-154-2/+56
| | | | Reviewed-by: Alex Deucher <[email protected]>
* r600g: enable MSAA on evergreen by defaultMarek Olšák2012-08-151-3/+24
| | | | v2: add the DRM version check
* r600g: implement copying between MSAA texturesMarek Olšák2012-08-151-4/+10
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* r600g: implement MSAA color resolveMarek Olšák2012-08-156-3/+177
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