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* radeonsi: mark descriptor loads as using dynamically uniform indicesNicolai Hähnle2016-05-051-5/+17
| | | | | | | | This tells LLVM to always use SMEM loads for descriptors. It fixes a regression in piglit's arb_shader_storage_buffer_object/execution/indirect.shader_test that was caused by LLVM r268259 (but the proper fix is really here in Mesa). Reviewed-by: Marek Olšák <[email protected]>
* i965/fs: Don't follow pow with an instruction with two dest regs.Matt Turner2016-05-051-0/+18
| | | | | | | | | | | | | | | | | Beginning with commit 7b208a73, Unigine Valley began hanging the GPU on Gen >= 8 platforms. Evidently that commit allowed the scheduler to make different choices that somehow finally ran afoul of a hardware bug in which POW and FDIV instructions may not be followed by an instruction with two destination registers (including compressed instructions). I presume the conditions are more complex than that, but the internal hardware bug report (BDWGFX bug_de 1696294) does not contain much more information. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94924 Reviewed-by: Topi Pohjolainen <[email protected]> [v1] Tested-by: Mark Janes <[email protected]> [v1] Reviewed-by: Francisco Jerez <[email protected]>
* swr: Remove stall waiting for core query counters.Bruce Cherniak2016-05-054-124/+81
| | | | | | | | When gathering query results, swr_gather_stats was unnecessarily stalling the entire pipeline. Results are now collected asynchronously, with a fence marking completion. Reviewed-By: George Kyriazis <[email protected]>
* mesa/ubo: add missing compute cases for ubo/atomic buffersDave Airlie2016-05-051-0/+6
| | | | | | | This fixes: GL43-CTS.compute_shader.resource-ubo Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa/compute: drop pointless casts.Dave Airlie2016-05-051-3/+3
| | | | | | | | We already are a GLintptr, casting won't help. Reviewed-by: Alejandro Piñeiro <[email protected]> Reviewed-by: Anuj Phogat <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
* mesa: remove null check before freeThomas Hindoe Paaboel Andersen2016-05-052-4/+2
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* freedreno: remove null check before freeThomas Hindoe Paaboel Andersen2016-05-051-2/+1
| | | | Reviewed-by: Eduardo Lima Mitev <[email protected]>
* nir: fix assert for wildcard pairsThomas Hindoe Paaboel Andersen2016-05-051-1/+1
| | | | | | | | | The assert was null checking dest_arr_parent twice. The intention seems to be to check both dest_ and src_. Added in d3636da9 Reviewed-by: Eduardo Lima Mitev <[email protected]>
* glapi: fix parameter type for GetSamplerParameterIuivEXT() in es_EXT.xmlBrian Paul2016-05-041-2/+2
| | | | | | | | | | The function returns GLuint, not GLfloat values. v2: also fix the OES function Cc: "11.2" <[email protected]> Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
* mesa: include texture format in glGenerateMipmap error messageBrian Paul2016-05-041-1/+2
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* main: uses casts to silence some _mesa_debug() format warningsBrian Paul2016-05-041-4/+6
| | | | | | | Silences warnings with 32-bit Linux gcc builds and MinGW which doesn't recognize the ‘t’ conversion character. Reviewed-by: Sinclair Yeh <[email protected]>
* docs: Mark GL_ARB_query_buffer_object as done for i965/hsw+Jordan Justen2016-05-042-1/+2
| | | | Signed-off-by: Jordan Justen <[email protected]>
* i965: Implement ARB_query_buffer_object for HSW+Jordan Justen2016-05-048-3/+501
| | | | | | | | | | | | | | | v2: * Declare loop index variable at loop site (idr) * Make arrays of MI_MATH instructions 'static const' (idr) * Remove commented debug code (idr) * Updated comment in set_query_availability (Ken) * Replace switch with if/else in hsw_result_to_gpr0 (Ken) * Only divide GL_FRAGMENT_SHADER_INVOCATIONS_ARB by 4 on hsw and gen8 (Ken) Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]> Reviewed-by: Ian Romanick <[email protected]>
* i965/gen6+: Add load register immediate helper functionsJordan Justen2016-05-042-0/+36
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/hsw+: Add support for copying a registerJordan Justen2016-05-043-0/+18
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965/gen6+: Add support for storing immediate data into a bufferJordan Justen2016-05-043-0/+50
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add MI_MATH reg defs for HSW+Jordan Justen2016-05-041-0/+38
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add brw_store_register_mem32Jordan Justen2016-05-042-0/+28
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Use offset instead of index in brw_store_register_mem64Jordan Justen2016-05-045-54/+52
| | | | | | | | | | This matches the byte based offset of brw_load_register_mem*. The function is also moved into intel_batchbuffer.c like brw_load_register_mem*. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* r600,compute: create vtx buffer for text + rodataJan Vesely2016-05-041-2/+10
| | | | | | | Reserve buffer id 2 Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Tom Stellard <[email protected]>
* freedreno: allow ctx->draw_vbo to failRob Clark2016-05-045-30/+37
| | | | | | | Pretty much only happens if shader variant compile fails. But in this case, if we haven't emitted cmdstream, we don't want to set needs_flush. Signed-off-by: Rob Clark <[email protected]>
* freedreno: move shader-stage dirty bits to global dirty flagRob Clark2016-05-048-59/+41
| | | | | | | | | | | This was always a bit overly complicated, and had some issues (like ctx->prog.dirty not getting reset at the end of the batch). It also required some special hacks to avoid resetting dirty state on binning pass. So just move it all into ctx->dirty (leaving some free bits for future shader stages), and make FD_DIRTY_PROG just be the union of all FD_SHADER_DIRTY_*. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: fix bogus offset for f32x24s8 stencil restoreRob Clark2016-05-041-4/+5
| | | | | | fixes: $piglit/bin/fbo-clear-formats GL_ARB_depth_buffer_float Signed-off-by: Rob Clark <[email protected]>
* freedreno: add some debug_asserts() to catch insane offsetsRob Clark2016-05-041-0/+2
| | | | | | | Ofc won't catch *all* faults, but at least helpful for catching offsets which are completely bogus. Signed-off-by: Rob Clark <[email protected]>
* freedreno/a4xx: deal with VS which do not write positionRob Clark2016-05-041-0/+7
| | | | | | | | Fixes $piglit/bin/glsl-1.40-tf-no-position a3xx may need similar? Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: remove a couple redundant is_flow()sRob Clark2016-05-042-2/+2
| | | | | | | Now that the opc's encode the instruction category (making them unique) we no longer need to check the category in addition to the opc. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: cp small negative integers tooRob Clark2016-05-041-1/+2
| | | | Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: fix # of registersRob Clark2016-05-041-1/+1
| | | | | | | The instruction encoding allows for more registers, but at least on a3xx/a4xx they don't actually exist. Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: lower immeds to constRob Clark2016-05-043-4/+80
| | | | | | | | | | | | | | | | | Helps reduce register pressure and instruction counts for immediates that would otherwise require a mov into gpr. total instructions in shared programs: 4455332 -> 4369297 (-1.93%) total dwords in shared programs: 8807872 -> 8614432 (-2.20%) total full registers used in shared programs: 263062 -> 250846 (-4.64%) total half registers used in shader programs: 9845 -> 9845 (0.00%) total const registers used in shared programs: 1029735 -> 1466993 (42.46%) half full const instr dwords helped 0 10415 0 17861 5912 hurt 0 1157 21458 947 33 Signed-off-by: Rob Clark <[email protected]>
* freedreno/ir3: add ir3_cp_ctxRob Clark2016-05-043-12/+22
| | | | | | Needed in next commit.. just split out to reduce noise. Signed-off-by: Rob Clark <[email protected]>
* add REVIEWERS and get_reviewer.pl scriptRob Clark2016-05-042-0/+2407
| | | | | | | | | | | | | | | | | | | | | | | | | | Copied from linux kernel (where it is called MAINTAINERS and get_maintainer.pl), with minimal changes to script (to recognize mesa src tree rather than linux kernel src tree, and to avoid accidentaly CC'ing Linus Torvalds on mesa patches), and slimmed down MAINTAINER file syntax to recognize that we don't really have subsystem "maintainers" in the same sense as the linux kernel (ie. no different mailing lists and git trees per subsystem). The main point is to automate slapping on the correct CC's for patches via git's --cc-cmd feature, more than anything else. I didn't attempt to fully populate the REVIEWERS file, by a long shot. This is an opt-in system and anyone else can add their own entries. To utilize: git send-email --cc-cmd ./scripts/get_reviewer.pl ... or to configure it to be the default: git config sendemail.cccmd ./scripts/get_reviewer.pl Signed-off-by: Rob Clark <[email protected]>
* nouveau/video: properly detect the decoder class for availability checksIlia Mirkin2016-05-041-8/+17
| | | | | | | | | | | The kernel is now more strict with the class ids it exposes, so we need to check the G98 and MCP89 classes as well as the GT215 class. This effectively caused us to decide there were no decoding capabilities on newer kernel for VP3 chips. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95251 Signed-off-by: Ilia Mirkin <[email protected]> Cc: "11.2" <[email protected]>
* i965: Delete stale perf_debug().Kenneth Graunke2016-05-041-2/+0
| | | | MOCS for 3DSTATE_SO_BUFFER has existed for ages.
* i965: Silence unused variable warningKenneth Graunke2016-05-041-2/+0
| | | | I added this when deleting some unnecessary code in a rebase.
* mesa/main: handle double uniform matrices properlyJuan A. Suarez Romero2016-05-041-1/+1
| | | | | | | | When computing the offset in the uniform storage table, take into account the size multiplier so double precision matrices are handled correctly. Signed-off-by: Juan A. Suarez Romero <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* nir: Separate 32 and 64-bit fmod loweringSamuel Iglesias Gonsálvez2016-05-043-4/+6
| | | | | | | | Split 32-bit and 64-bit fmod lowering as the drivers might need to lower them separately inside NIR depending on the HW support. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* nir/lower_double_ops: lower mod()Samuel Iglesias Gonsálvez2016-05-042-1/+31
| | | | | | | | | | | There are rounding errors with the division in i965 that affect the mod(x,y) result when x = N * y. Instead of returning '0' it was returning 'y'. This lowering pass fixes those cases. Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Define GEN_GE/GEN_LE macros in terms of GEN_LT.Matt Turner2016-05-031-2/+3
| | | | | | | | GEN_LT has a straightforward implementation on which we can build the GEN_GE and GEN_LE macros. Suggested-by: Ilia Mirkin <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Add disassembler support for remaining opcodes.Matt Turner2016-05-032-18/+92
| | | | | | | | | For opcodes that changed meaning on different generations, we store a pointer to a secondary table and the table's size in a tagged union in place of the mnemonic and number of sources. Acked-by: Francisco Jerez <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Make opcode_descs and gen_from_devinfo() static.Matt Turner2016-05-032-6/+2
| | | | | | | | | The previous commit replaced direct uses of opcode_descs with calls to the wrapper function, which should be the only method of accessing opcode_descs's data. As a result gen_from_devinfo() can also be made static. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Actually check whether the opcode is supported.Matt Turner2016-05-032-4/+3
| | | | Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Merge inst_info and opcode_desc tables.Matt Turner2016-05-035-149/+73
| | | | | | | I merged opcode_desc into inst_info (instead of the other way around) because inst_info was sorted by opcode number. Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Move inst_info from brw_eu_validate.c to brw_eu.c.Matt Turner2016-05-033-245/+249
| | | | | | | | | Drop the uses of 'enum gen' to a plain int, so that we don't have to expose the bitfield definitions and GEN_GE/GEN_LE macros to other users of brw_eu.h. As a result, s/.gen/.gens/ to avoid confusion with devinfo->gen. Reviewed-by: Kenneth Graunke <[email protected]>
* i965/disasm: Wrap opcode_desc look-up in a function.Francisco Jerez2016-05-035-14/+42
| | | | | | | | | | | | | | The function takes a device info struct as argument in addition to the opcode number in order to disambiguate between multiple opcode_desc entries for different instructions with the same opcode number. Reviewed-by: Iago Toral Quiroga <[email protected]> [v1] [v2] mattst88: Put brw_opcode_desc() in brw_eu.c instead of moving it there in a later patch. Reviewed-by: Kenneth Graunke <[email protected]> [v2] [v3] mattst88: Return NULL if opcode >= ARRAY_SIZE(opcode_descs) Reviewed-by: Matt Turner <[email protected]>
* i965: Pass devinfo pointer to is_3src() helpers.Francisco Jerez2016-05-038-10/+11
| | | | | | | | | | | | | | This is not strictly required for the following changes because none of the three-source opcodes we support at the moment in the compiler back-end has been removed or redefined, but that's likely to change in the future. In any case having hardware instructions specified as a pair of hardware device and opcode number explicitly in all cases will simplify the opcode look-up interface introduced in a subsequent commit, since the opcode number alone is in general ambiguous. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Pass devinfo pointer to brw_instruction_name().Francisco Jerez2016-05-034-4/+5
| | | | | | | | | | | | A future series will implement support for an instruction that happens to have the same opcode number as another instruction we support already on a disjoint set of hardware generations. In order to disambiguate which instruction it is brw_instruction_name() will need some way to find out which device we are generating code for. Reviewed-by: Iago Toral Quiroga <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* i965: Write a scalar TCS backend that runs in SINGLE_PATCH mode.Kenneth Graunke2016-05-037-15/+510
| | | | | | | | | | | | | | | | | | | | | | | Unlike most shader stages, the Hull Shader hardware makes us explicitly tell it how many threads to dispatch and manually configure the channel mask. One perk of this is that we have a lot of flexibility - we can run it in either SIMD4x2 or SIMD8 mode. Treating it as SIMD8 means that shaders with 8 or fewer output vertices (which is overwhemingly the common case) can be handled by a single thread. This has several intriguing properties: - Accessing input arrays with gl_InvocationID as the index is a simple SIMD8 URB read with g1 as the header. No indirect addressing required. - Barriers are no-ops. - We could potentially do output shadowing to combine writes, as the concurrency concerns are gone. (We don't do this yet, though.) v2: Drop first_non_payload_grf change, as it was always adding 0 (caught by Jordan Justen). Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* i965: Rework the TCS passthrough shader to use NIR.Kenneth Graunke2016-05-033-56/+85
| | | | | | | | | | | | | | | I'm about to implement a scalar TCS backend, and I'd rather not duplicate all of this code there. One change is that we now write the tessellation levels from all TCS threads, rather than just the first. This is pretty harmless, and was easier. The IF/ENDIF needed for that are gone; otherwise the generated code is basically identical. I chose to emit load/store intrinsics directly because it was easier. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Jordan Justen <[email protected]>
* gallium/util: change assertion to conditional in util_bitmask_destroy()Brian Paul2016-05-031-4/+4
| | | | | | | | If we fail to create a context in the VMware driver we call this function unconditionally to free a bunch of bit vectors. Instead of asserting on a null pointer, just no-op. Reviewed-by: Jose Fonseca <[email protected]>
* cso: null-out previously bound sampler statesBrian Paul2016-05-031-1/+3
| | | | | | | | | | | | | If, for example, we previously had 2 sampler states bound and now we are binding one, we'd leave the second sampler state unchanged. This change nulls-out the second sampler state in this situation. We're already doing the same thing for sampler views. This silences an occasional warning issued by the VMware driver when the number of sampler views and sampler states disagreed. Reviewed-by: Charmaine Lee <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
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