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* mesa: Use realloc() instead of _mesa_realloc() and remove the latter.Matt Turner2014-09-247-30/+8
| | | | Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
* mesa: Remove duplicate _mesa_{init,free}_shader_state prototypes.Matt Turner2014-09-241-7/+0
| | | | Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
* gallivm: Wrap deleted inlcude in if HAVE_LLVM < 0x0306Tom Stellard2014-09-241-0/+2
| | | | This was missed in 8f4ee56.
* i965: Add and use functions to get next/prev blocks.Matt Turner2014-09-246-20/+73
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Call insert and remove functions from exec_node directly.Matt Turner2014-09-243-14/+11
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Make instruction lists local to the bblocks.Matt Turner2014-09-2412-92/+115
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/cfg: Add note about double-loop macros and break behavior.Matt Turner2014-09-241-0/+6
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Replace initialization loops with memset().Matt Turner2014-09-242-15/+5
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/vec4: Don't iterate between blocks with inst->next/prev.Matt Turner2014-09-241-21/+9
| | | | | | The register coalescing portion of this patch hurts three shaders in Guacamelee by one instruction each, but examining the diff makes me believe that what we were generating was (perhaps harmlessly) incorrect.
* i965/fs: Don't iterate between blocks with inst->next/prev.Matt Turner2014-09-245-47/+34
| | | | | | When instruction lists are per-basic block, this won't work. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/cfg: Add macros to iterate through a block given a starting point.Matt Turner2014-09-241-0/+10
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/fs: Make count_to_loop_end() use basic blocks.Matt Turner2014-09-241-15/+16
| | | | | | | When the instructions aren't in a flat list, this wouldn't have worked. Also, this should be faster. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/vec4: Don't use instruction list after calculating the cfg.Matt Turner2014-09-245-14/+15
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/fs: Don't use instruction list after calculating the cfg.Matt Turner2014-09-243-22/+22
| | | | | | | | The only trick is changing a break into a return true in register coalescing, since the macro is actually a double loop, and break will do something different than you expect. (Wish I'd realized that earlier!) Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Remove now unneeded calls to calculate_cfg().Matt Turner2014-09-2412-39/+4
| | | | | | | Now that nothing invalidates the CFG, we can calculate_cfg() immediately after emit_fb_writes()/emit_thread_end() and never again. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Remove cfg-invalidating parameter from invalidate_live_intervals.Matt Turner2014-09-2420-40/+34
| | | | | | Everything has been converted to preserve the CFG. Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Preserve the CFG in instruction scheduling.Matt Turner2014-09-241-32/+42
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/vec4: Preserve CFG in spill_reg().Matt Turner2014-09-244-38/+56
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/vec4: Preserve the CFG in a few more places.Matt Turner2014-09-241-7/+16
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965/fs: Preserve the CFG in a few more places.Matt Turner2014-09-242-15/+21
| | | | Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
* i965: Restructure debug flagsKristian Høgsberg2014-09-242-60/+60
| | | | | | | | | | | This cleans up the debug flags to be consistently indented, use bit shifting instead of hex-values and fixes a bug where the new DEBUG_NO8 flag used the same value as the DEBUG_VUE flag. This was hidden by the numbers not being aligned. Also removes gaps in the range where DEBUG_IOCTL (0x4) and DEBUG_REGION (0x400) used to be. Signed-off-by: Kristian Høgsberg <krh@bitplanet.net> Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
* gallivm: Disable gallivm to fix build with LLVM 3.6Tom Stellard2014-09-241-0/+10
| | | | | | | | | | | | | | | | LLVM commit r218316 removes the JITMemoryManager class, which is the parent for a seemingly important class in gallivm. In order to fix the build, I've wrapped most of lp_bld_misc.cpp in if HAVE_LLVM < 0x0306 and modifyed the lp_build_create_jit_compiler_for_module() function to return false for 3.6 and newer which effectively disables the gallivm functionality. I realize this is overkill, but I could not come up with a simple solution to fix the build. Also, since 3.6 will be the first release without the old JIT, it would be really great if we could move gallivm to use the C API only for accessing MCJIT. There is still time before the 3.6 release to extend the C API in case it is missing some functionality that is required by gallivm.
* gallium/rbug: correctly unreference a sampler viewMarek Olšák2014-09-241-2/+1
| | | | | | | This fixes heap corruption. The sampler view can be bound in the context, so we cannot call destroy directly. Reviewed-by: Brian Paul <brianp@vmware.com>
* gallium/rbug: unlock a mutex in rbug_create_queryMarek Olšák2014-09-241-3/+5
| | | | Reviewed-by: Brian Paul <brianp@vmware.com>
* radeonsi: remove old cache flushing codeMarek Olšák2014-09-244-66/+1
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi/compute: do CS partial flush with si_emit_cache_flushMarek Olšák2014-09-243-6/+9
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* radeonsi/compute: flush caches with si_emit_cache_flushMarek Olšák2014-09-243-23/+32
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* radeonsi/compute: directly emit CONTEXT_CONTROLMarek Olšák2014-09-241-1/+5
| | | | | Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
* radeonsi: properly destroy the GS copy shader and scratch_bo for computeMarek Olšák2014-09-242-3/+8
| | | | | Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: release GS rings at context destructionMarek Olšák2014-09-241-0/+2
| | | | | Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: don't use pipe_constant_buffer for GS ringsMarek Olšák2014-09-244-26/+22
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: don't pass the context to the shader translatorMarek Olšák2014-09-244-22/+18
| | | | | | This should prevent accessing context state there. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: don't snoop currently-bound GS shader when compiling ESMarek Olšák2014-09-243-16/+101
| | | | | | | | | Instead, pass the layout of GS inputs in memory to the ES using the shader key. Only 64 bits are needed to represent the layout in the key. Mixing and matching different VS and GS shaders should now always work. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: shorten si_pipe_* prefixes to si_*Marek Olšák2014-09-248-58/+57
| | | | | | | This was the original naming convention in r600g and it somehow crept into radeonsi. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: merge si_pipe_shader into si_shaderMarek Olšák2014-09-245-92/+90
| | | | | | One is part of the other anyway. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: disable gl_SampleMask fragment shader output if MSAA is disabledMarek Olšák2014-09-241-3/+18
| | | | | | This fixes piglit: arb_sample_shading-builtin-gl-sample-mask 0 Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: only update MSAA-specific framebuffer state if nr_samples is changedMarek Olšák2014-09-241-23/+27
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: move DB_SHADER_CONTROL into db_render_stateMarek Olšák2014-09-244-13/+18
| | | | | | | | | I will need this for fixing sample shading with 1 sample. The good news is that all shader pm4 states no longer use the current context state, so we can generate the pm4 states outside of draw_vbo if needed. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: set KILL_ENABLE during shader compilation, remove uses_kill flagMarek Olšák2014-09-243-5/+5
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: remove shader.ps_conservative_z, set db_shader_control insteadMarek Olšák2014-09-243-8/+4
| | | | | | Also set the field on SI too. It's not just specific to CIK. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: move DB registers from draw_vbo into new db_render_stateMarek Olšák2014-09-245-66/+82
| | | | | | It's called db_misc_state in r600g. Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: remove unused variable si_pipe_shader::sprite_coord_enableMarek Olšák2014-09-242-2/+0
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* radeonsi: document what si_descriptors.c doesMarek Olšák2014-09-241-0/+11
| | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
* r300g: implement MSAA copies by resolving and upsamplingMarek Olšák2014-09-241-2/+3
| | | | There's no other way. It will use hw resolve + blit.
* st/mesa: redefine mapping from VARYING_SLOT_TEXi/PNTC/VARi to TGSI GENERIC[i]Marek Olšák2014-09-243-22/+52
| | | | | | | | | | | Generic varyings in TGSI were based on the value of VARYING_SLOT_TEX0, so VAR0 was always GENERIC[22] (with tessellation patches). Some drivers might not be able to cope with that. This commit defines a proper mapping, so that PNTC is GENERIC[8] and VAR0 is GENERIC[9]. Reviewed-by: Brian Paul <brianp@vmware.com>
* st/mesa: don't set coord_enable for gl_PointCoord if using TGSI_SEMANTIC_PCOORDMarek Olšák2014-09-241-1/+2
| | | | | | This was missed when Christoph Bumiller added PIPE_CAP_TGSI_TEXCOORD. Reviewed-by: Brian Paul <brianp@vmware.com>
* st/mesa: use UniformBooleanTrue in glsl_to_tgsiMarek Olšák2014-09-241-4/+1
| | | | | | | Just for consistency. This doesn't fix anything as the original code was already pretty good. Reviewed-by: Brian Paul <brianp@vmware.com>
* st/mesa: drop dependence on API profile in st_init_extensionsMarek Olšák2014-09-244-14/+11
| | | | | | | The extensions and limits being set in the conditional block are core-only anyway and don't have any effect on other profiles. Reviewed-by: Brian Paul <brianp@vmware.com>
* mesa: allow forcing >=3.1 compatibility contexts with MESA_GL_VERSION_OVERRIDEMarek Olšák2014-09-241-6/+10
| | | | | | | | | | E.g. the 4.0 compatibility profile can be forced with: MESA_GL_VERSION_OVERRIDE=4.0COMPAT Some tests that I have require 4.0 compatibility. Reviewed-by: Brian Paul <brianp@vmware.com>
* mesa: don't set ES versions to GLSLVersion in _mesa_init_constantsMarek Olšák2014-09-242-11/+3
| | | | | | | No place in Mesa expects an ES version there. Drivers don't even set it like this. Reviewed-by: Brian Paul <brianp@vmware.com>