| Commit message (Collapse) | Author | Age | Files | Lines |
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Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
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Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
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This was missed in 8f4ee56.
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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The register coalescing portion of this patch hurts three shaders in
Guacamelee by one instruction each, but examining the diff makes me
believe that what we were generating was (perhaps harmlessly) incorrect.
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When instruction lists are per-basic block, this won't work.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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When the instructions aren't in a flat list, this wouldn't have worked.
Also, this should be faster.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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The only trick is changing a break into a return true in register
coalescing, since the macro is actually a double loop, and break will do
something different than you expect. (Wish I'd realized that earlier!)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Now that nothing invalidates the CFG, we can calculate_cfg() immediately
after emit_fb_writes()/emit_thread_end() and never again.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Everything has been converted to preserve the CFG.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
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This cleans up the debug flags to be consistently indented, use bit
shifting instead of hex-values and fixes a bug where the new DEBUG_NO8 flag
used the same value as the DEBUG_VUE flag. This was hidden by the numbers not
being aligned. Also removes gaps in the range where DEBUG_IOCTL (0x4) and
DEBUG_REGION (0x400) used to be.
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
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LLVM commit r218316 removes the JITMemoryManager class, which is
the parent for a seemingly important class in gallivm. In order to
fix the build, I've wrapped most of lp_bld_misc.cpp in
if HAVE_LLVM < 0x0306 and modifyed the
lp_build_create_jit_compiler_for_module() function to return false
for 3.6 and newer which effectively disables the gallivm functionality.
I realize this is overkill, but I could not come up with a simple
solution to fix the build. Also, since 3.6 will be the first release
without the old JIT, it would be really great if we could
move gallivm to use the C API only for accessing MCJIT. There
is still time before the 3.6 release to extend the C API in
case it is missing some functionality that is required by gallivm.
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This fixes heap corruption. The sampler view can be bound in the context,
so we cannot call destroy directly.
Reviewed-by: Brian Paul <brianp@vmware.com>
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Reviewed-by: Brian Paul <brianp@vmware.com>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Cc: 10.2 10.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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This should prevent accessing context state there.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Instead, pass the layout of GS inputs in memory to the ES using the shader
key. Only 64 bits are needed to represent the layout in the key.
Mixing and matching different VS and GS shaders should now always work.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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This was the original naming convention in r600g and it somehow crept
into radeonsi.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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One is part of the other anyway.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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This fixes piglit: arb_sample_shading-builtin-gl-sample-mask 0
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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I will need this for fixing sample shading with 1 sample.
The good news is that all shader pm4 states no longer use the current context
state, so we can generate the pm4 states outside of draw_vbo if needed.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Also set the field on SI too. It's not just specific to CIK.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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It's called db_misc_state in r600g.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
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There's no other way. It will use hw resolve + blit.
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Generic varyings in TGSI were based on the value of VARYING_SLOT_TEX0, so VAR0
was always GENERIC[22] (with tessellation patches). Some drivers might not
be able to cope with that.
This commit defines a proper mapping, so that PNTC is GENERIC[8] and VAR0 is
GENERIC[9].
Reviewed-by: Brian Paul <brianp@vmware.com>
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This was missed when Christoph Bumiller added PIPE_CAP_TGSI_TEXCOORD.
Reviewed-by: Brian Paul <brianp@vmware.com>
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Just for consistency. This doesn't fix anything as the original code was
already pretty good.
Reviewed-by: Brian Paul <brianp@vmware.com>
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The extensions and limits being set in the conditional block are core-only
anyway and don't have any effect on other profiles.
Reviewed-by: Brian Paul <brianp@vmware.com>
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E.g. the 4.0 compatibility profile can be forced with:
MESA_GL_VERSION_OVERRIDE=4.0COMPAT
Some tests that I have require 4.0 compatibility.
Reviewed-by: Brian Paul <brianp@vmware.com>
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No place in Mesa expects an ES version there.
Drivers don't even set it like this.
Reviewed-by: Brian Paul <brianp@vmware.com>
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