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* docs: s/Aptril/April/Brian Paul2019-04-191-1/+1
* lima/ppir: support ppir_op_ceilErico Nunes2019-04-193-0/+14
* radv: Support VK_EXT_inline_uniform_block.Bas Nieuwenhuizen2019-04-195-15/+124
* ac/nir: use the new raw/struct SSBO atomic intrisics for comp_swapSamuel Pitoiset2019-04-191-2/+1
* ac/nir: only use the new raw/struct SSBO atomic intrinsics with LLVM 9+Samuel Pitoiset2019-04-191-1/+4
* ac/nir: only use the new raw/struct image atomic intrinsics with LLVM 9+Samuel Pitoiset2019-04-191-1/+4
* iris: Be less aggressive at postdraw work skippingKenneth Graunke2019-04-181-28/+36
* intel/fs: Account for live range lengths in spill costsJason Ekstrand2019-04-181-1/+13
* virgl/vtest: bump up protocol version + support encoded transfersGurchetan Singh2019-04-183-3/+12
* virgl/vtest: wait after issuing a transfer getGurchetan Singh2019-04-181-2/+3
* virgl/vtest: modify sending and receiving data for shared memoryGurchetan Singh2019-04-181-4/+35
* virgl/vtest: receive and handle shared memory fdGurchetan Singh2019-04-182-7/+55
* virgl/vtest: plumb support for shared memoryGurchetan Singh2019-04-183-6/+10
* virgl/vtest: add utilities for receiving fdsGurchetan Singh2019-04-181-0/+43
* virgl/vtest: execute a transfer_get when flushing the front bufferGurchetan Singh2019-04-181-22/+21
* virgl: wait after a flushGurchetan Singh2019-04-183-6/+12
* anv: fix uninitialized pthread cond clock domainLionel Landwerlin2019-04-181-1/+1
* .gitignore: Remove autotool artifactsKristian H. Kristensen2019-04-181-21/+0
* v3d: Fix atomic cmpxchg in shaders on hardware.Eric Anholt2019-04-181-3/+13
* v3d: Fix an invalid reuse of flags generation from before a thrsw.Eric Anholt2019-04-181-0/+4
* anv: Drop some unneeded ANV_FROM_HANDLE for physical devicesJason Ekstrand2019-04-181-6/+0
* anv: Re-sort the GetPhysicalDeviceFeatures2 switch statementJason Ekstrand2019-04-181-17/+17
* radeonsi/gfx9: use the correct condition for the DPBB + QUANT_MODE workaroundMarek Olšák2019-04-181-4/+4
* nir/algebraic: Strength reduce some compares of x and -xIan Romanick2019-04-181-0/+3
* nir/algebraic: Fix some 1-bit Boolean weirdnessIan Romanick2019-04-181-0/+3
* nir/algebraic: Replace a pattern where iand with a Boolean is used as a bcselIan Romanick2019-04-181-0/+4
* nir/algebraic: Recognize open-coded copysign(1.0, a)Ian Romanick2019-04-181-0/+6
* intel/fs: Generate better code for fsign multiplied by a valueIan Romanick2019-04-181-0/+43
* intel/fs: Add a scale factor to emit_fsignIan Romanick2019-04-182-12/+77
* intel/fs: Refactor code generation for nir_op_fsign to its own functionIan Romanick2019-04-182-65/+65
* intel/fs: Eliminate dead code firstIan Romanick2019-04-181-0/+8
* freedreno: Fix format string warningKristian H. Kristensen2019-04-181-1/+1
* freedreno/a6xx: Add helper for incrementing regidKristian H. Kristensen2019-04-181-1/+10
* freedreno: Use enum values from matching enumKristian H. Kristensen2019-04-182-3/+3
* freedreno/a2xx: Fix redundant if statementKristian H. Kristensen2019-04-181-16/+14
* freedreno/ir3: Mark ir3_context_error() as NORETURNKristian H. Kristensen2019-04-182-3/+3
* nir: Add a nir_src_as_intrinsic() helperJason Ekstrand2019-04-185-51/+19
* nir: Rework nir_src_as_alu_instr to not take a pointerJason Ekstrand2019-04-184-26/+18
* nir: Drop "struct" from some nir_* declarationsJason Ekstrand2019-04-183-11/+11
* anv: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-181-0/+11
* i965: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-182-0/+6
* iris: implement WaEnableStateCacheRedirectToCSLionel Landwerlin2019-04-182-0/+12
* anv/device: expose VK_KHR_shader_float16_int8 in gen8+Iago Toral Quiroga2019-04-182-0/+10
* anv/pipeline: support Float16 and Int8 SPIR-V capabilities in gen8+Iago Toral Quiroga2019-04-181-0/+2
* compiler/spirv: move the check for Int8 capabilityIago Toral Quiroga2019-04-181-4/+3
* intel/compiler: validate region restrictions for mixed float modeIago Toral Quiroga2019-04-182-0/+880
* intel/compiler: validate conversions between 64-bit and 8-bit typesIago Toral Quiroga2019-04-182-0/+105
* intel/compiler: validate region restrictions for half-float conversionsIago Toral Quiroga2019-04-182-1/+270
* intel/compiler: also set F execution type for mixed float mode in BDWIago Toral Quiroga2019-04-181-16/+20
* intel/compiler: implement SIMD16 restrictions for mixed-float instructionsIago Toral Quiroga2019-04-181-0/+72
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