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* anv: Use corresponding type from the vector allocationLionel Landwerlin2019-05-092-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We didn't notice this issue much because the 2 struct share a similar layout, expect for the additional fields... We run into that issue in Anv : ==15236== Invalid write of size 8 ==15236== at 0x8CF3939C: anv_state_table_expand_range (anv_allocator.c:211) ==15236== by 0x8CF394D5: anv_state_table_grow (anv_allocator.c:264) ==15236== by 0x8CF3967E: anv_state_table_add (anv_allocator.c:312) ==15236== by 0x8CF3B13C: anv_state_pool_alloc_no_vg (anv_allocator.c:1167) ==15236== by 0x8CF3B2B0: anv_state_pool_alloc (anv_allocator.c:1190) ==15236== by 0x8CF60871: alloc_surface_state (anv_image.c:1122) ==15236== by 0x8CF61FF9: anv_CreateImageView (anv_image.c:1519) ==15236== by 0x8BCBD2ED: vkCreateImageView (trampoline.c:1358) ==15236== Address 0x8994ef10 is 0 bytes after a block of size 128 alloc'd ==15236== at 0x4C2FB0F: malloc (in /usr/lib/valgrind/vgpreload_memcheck-amd64-linux.so) ==15236== by 0x8D2578E6: u_vector_init (u_vector.c:47) ==15236== by 0x8CF3929A: anv_state_table_init (anv_allocator.c:168) ==15236== by 0x8CF3A99A: anv_state_pool_init (anv_allocator.c:921) ==15236== by 0x8CF56517: anv_CreateDevice (anv_device.c:1909) ==15236== by 0x8BCB4FBA: terminator_CreateDevice (loader.c:6073) ==15236== by 0x8DD2CB3D: ??? (in /home/djdeath/.steam/ubuntu12_64/libVkLayer_steam_fossilize.so) ==15236== by 0x8DF4D241: vkCreateDevice (in /home/djdeath/.steam/ubuntu12_64/steamoverlayvulkanlayer.so) ==15236== by 0x8BCB35C6: loader_create_device_chain (loader.c:5449) ==15236== by 0x8BCBC230: vkCreateDevice (trampoline.c:838) v2: Rename mmap_cleanups to avoid confusion (Caio) v3: s/fail_mmap_cleanups/fail_cleanups/ (Caio) Signed-off-by: Lionel Landwerlin <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110648 Cc: <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* docs: update calendar, and news item and link release notes for 19.0.4Dylan Baker2019-05-093-7/+8
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* docs: Add SHA256 sums for mesa 19.0.4Dylan Baker2019-05-091-1/+2
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* Docs: add 19.0.4 release notesDylan Baker2019-05-091-0/+242
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* mesa: fix GL_PROGRAM_BINARY_RETRIEVABLE_HINT handlingPierre-Eric Pelloux-Prayer2019-05-092-4/+11
| | | | | | | | | | | | | | | When first implemented in fefd03e16c16 Mesa's behavior was aligned on behavior of Nvidia's driver. This caused a failing test in piglit but was ok since the specification is unclear on this subject. Nvidia's driver behavior has been modified because using version 410.104, the problematic test (program_binary_retrievable_hint) now passes. This commit defers BinaryRetrievableHint update until the next linking so the test passes on Mesa as well. Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Marek Olšák <[email protected]>
* nir: Initialize lower_flrp_progress everywhereIan Romanick2019-05-096-6/+6
| | | | | | | | | | | | | | | | I don't know why I thought NIR_PASS always set the progress variable. Derp. Fixes: d41cdef2a59 ("nir: Use the flrp lowering pass instead of nir_opt_algebraic") Reviewed-by: Brian Paul <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Coverity CID: 1444996 Coverity CID: 1444995 Coverity CID: 1444994 Coverity CID: 1444993 Coverity CID: 1444991 Coverity CID: 1444989
* gallium: fix typo in commentEric Engestrom2019-05-091-1/+1
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* meson: fix a couple typos in commentsEric Engestrom2019-05-091-3/+3
| | | | Signed-off-by: Eric Engestrom <[email protected]>
* i965_asm: avoid free()ing uninitialized pointersEric Engestrom2019-05-091-1/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* i965_asm: fix memleakEric Engestrom2019-05-091-0/+1
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* radv: fix setting the number of rectangles when it's dyanmicSamuel Pitoiset2019-05-091-4/+6
| | | | | | | | | | We need to know the number of rectangles. This fixes new CTS dEQP-VK.draw.discard_rectangles.dynamic_*. Fixes: 5db0bf99944 ("radv: Implement VK_EXT_discard_rectangles.") Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* iris: Reorganise execbuf to have a single point of failureChris Wilson2019-05-081-27/+20
| | | | | | | | | | | Propagate the failure from GEM_EXECBUFFER2, cleanup then report failure if need be. We retain the current behaviour to abort() at the first sign of trouble -- for a non-robustness context, arguably this is the right thing to do as the client cannot recover, and the system state is lost. How to properly integrate with KHR_robustness and reset-strategy is left as a future exercise. Reviewed-by: Kenneth Graunke <[email protected]>
* drm-uapi: Update i915_drm.h for I915_CONTEXT_PARAM_RECOVERABLEChris Wilson2019-05-081-0/+20
| | | | | | | | | | | | Pull i915_drm.h to include kernel commit ba4fda620a5f7db521aa9e0262cf49854c1b1d9c Author: Chris Wilson <[email protected]> Date: Mon Feb 18 10:58:21 2019 +0000 drm/i915: Optionally disable automatic recovery after a GPU reset for improved resilience in handling GPU hangs.
* kmsro: add _dri.so to two of the kmsro drivers.Dave Airlie2019-05-091-2/+2
| | | | | | Fixes: 8cfc17bdda3 (kmsro: Add the rest of the current set of tinydrm drivers.) Reviewed-by: Eric Engestrom <[email protected]>
* iris: Report the same video memory settings as i965.Kenneth Graunke2019-05-082-2/+34
| | | | This just copy and pastes Ian's code from i965.
* gitlab-ci: add the vulkan overlay layer to the vulkan buildEric Engestrom2019-05-082-1/+4
| | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
* gitlab-ci: add the vulkan overlay layer to the vulkan buildEric Engestrom2019-05-081-0/+9
| | | | | | | | Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> [ Michel Dänzer: Take changes affecting the docker image from !299, plus remove the unzip package again before generating the image ]
* gitlab-ci: Don't install WINE packagesMichel Dänzer2019-05-081-3/+1
| | | | | | | They were just making the docker image larger for no benefit at this point. Reviewed-by: Eric Engestrom <[email protected]>
* gitlab-ci: Reorder jobs a bit to be generally ordered longer => shorterMichel Dänzer2019-05-081-33/+33
| | | | | | | This makes the longer jobs likely to run earlier, which can help the overall pipeline duration. Reviewed-by: Eric Engestrom <[email protected]>
* gitlab-ci: Build clover against all supported versions of LLVMMichel Dänzer2019-05-083-11/+21
| | | | | | | | | | | | | | | | And consolidate it all into a single job. It doesn't take much longer than a single version, thanks to ccache. Overall, this single job might be faster or at least use fewer CPU cycles than the two jobs before, while covering thrice as many versions of LLVM. v2: * Move "rm -rf _build" to meson-build.sh. * Set GALLIUM_DRIVERS the same way both times in the meson-clover job, for symmetry. Reviewed-by: Eric Engestrom <[email protected]> # v1
* gitlab-ci: Move meson job script to separate fileMichel Dänzer2019-05-082-25/+30
| | | | | | | | No functional change intended (except for no longer running meson --version separately, as the version appears early in meson's output anyway). Reviewed-by: Eric Engestrom <[email protected]>
* gitlab-ci: Remove superfluous comment about image tag counter suffixMichel Dänzer2019-05-081-3/+0
| | | | | | | | We really shouldn't ever need a suffix, otherwise it indicates a failure in coordination. :) In which case, it doesn't really matter how the tag is disambiguated. Reviewed-by: Eric Engestrom <[email protected]>
* meson: Force the use of config-tool for llvmDylan Baker2019-05-081-0/+1
| | | | | | | | | meson git now has a cmake find method for llvm, but it lacks a couple of features that we use from the config tool version. Until that reaches parity we need to use the config-tool version. CC: 19.0 19.1 <<[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* gallium/util: fix two MSVC compiler warningsBrian Paul2019-05-082-3/+3
| | | | | | | Remove stray const qualifier. s/unsigned/enum tgsi_semantic/ Reviewed-by: Roland Scheidegger <[email protected]>
* gallium/pp: s/uint/enum tgsi_semantic/ to fix MSVC warningBrian Paul2019-05-081-1/+1
| | | | Reviewed-by: Roland Scheidegger <[email protected]>
* noop: s/enum pipe_transfer_usage/unsigned/ to fix MSVC warningBrian Paul2019-05-081-1/+1
| | | | | | | The function pointer declaration in pipe_context uses unsigned for the bitmask. Reviewed-by: Roland Scheidegger <[email protected]>
* ddebug: fix a few MSVC compiler warningsBrian Paul2019-05-082-8/+9
| | | | | | | Don't return an expression in void functions. Replace an unsigned int with proper enum. Reviewed-by: Roland Scheidegger <[email protected]>
* glsl: s/GLboolean/bool/ to silence MSVC compiler warningBrian Paul2019-05-081-1/+1
| | | | | | It complains about mixing GLboolean and bool in the |= expression. Reviewed-by: Roland Scheidegger <[email protected]>
* nir/flrp: Reassociate add in flrp(±1, b, c) lowering pathIan Romanick2019-05-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this reassociation, this lowering path is still beneficial. Ice Lake total instructions in shared programs: 17220191 -> 17207181 (-0.08%) instructions in affected programs: 999871 -> 986861 (-1.30%) helped: 3703 HURT: 17 helped stats (abs) min: 1 max: 686 x̄: 3.52 x̃: 3 helped stats (rel) min: 0.09% max: 51.97% x̄: 2.21% x̃: 1.35% HURT stats (abs) min: 1 max: 9 x̄: 1.47 x̃: 1 HURT stats (rel) min: 0.08% max: 4.55% x̄: 0.78% x̃: 0.55% 95% mean confidence interval for instructions value: -4.01 -2.99 95% mean confidence interval for instructions %-change: -2.29% -2.11% Instructions are helped. total cycles in shared programs: 360871298 -> 360755040 (-0.03%) cycles in affected programs: 9931334 -> 9815076 (-1.17%) helped: 2388 HURT: 1569 helped stats (abs) min: 1 max: 10228 x̄: 93.54 x̃: 18 helped stats (rel) min: <.01% max: 74.11% x̄: 3.36% x̃: 1.07% HURT stats (abs) min: 1 max: 1917 x̄: 68.27 x̃: 22 HURT stats (rel) min: <.01% max: 44.90% x̄: 3.44% x̃: 1.72% 95% mean confidence interval for cycles value: -39.48 -19.28 95% mean confidence interval for cycles %-change: -0.86% -0.46% Cycles are helped. total spills in shared programs: 12355 -> 12159 (-1.59%) spills in affected programs: 295 -> 99 (-66.44%) helped: 2 HURT: 1 total fills in shared programs: 25398 -> 25207 (-0.75%) fills in affected programs: 288 -> 97 (-66.32%) helped: 2 HURT: 1 LOST: 3 GAINED: 44 Iron Lake total instructions in shared programs: 8169225 -> 8159729 (-0.12%) instructions in affected programs: 1025712 -> 1016216 (-0.93%) helped: 3352 HURT: 0 helped stats (abs) min: 1 max: 6 x̄: 2.83 x̃: 3 helped stats (rel) min: 0.15% max: 12.00% x̄: 1.51% x̃: 1.05% 95% mean confidence interval for instructions value: -2.86 -2.80 95% mean confidence interval for instructions %-change: -1.56% -1.46% Instructions are helped. total cycles in shared programs: 188656796 -> 188612280 (-0.02%) cycles in affected programs: 18633584 -> 18589068 (-0.24%) helped: 3085 HURT: 14 helped stats (abs) min: 2 max: 72 x̄: 14.45 x̃: 12 helped stats (rel) min: 0.02% max: 5.73% x̄: 0.73% x̃: 0.31% HURT stats (abs) min: 2 max: 4 x̄: 3.71 x̃: 4 HURT stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01% 95% mean confidence interval for cycles value: -14.55 -14.18 95% mean confidence interval for cycles %-change: -0.76% -0.69% Cycles are helped. GM45 total instructions in shared programs: 5026905 -> 5021856 (-0.10%) instructions in affected programs: 584169 -> 579120 (-0.86%) helped: 1776 HURT: 0 helped stats (abs) min: 1 max: 6 x̄: 2.84 x̃: 3 helped stats (rel) min: 0.15% max: 11.11% x̄: 1.43% x̃: 0.98% 95% mean confidence interval for instructions value: -2.88 -2.80 95% mean confidence interval for instructions %-change: -1.50% -1.37% Instructions are helped. total cycles in shared programs: 129047376 -> 129018918 (-0.02%) cycles in affected programs: 12941924 -> 12913466 (-0.22%) helped: 1722 HURT: 14 helped stats (abs) min: 4 max: 72 x̄: 16.56 x̃: 18 helped stats (rel) min: 0.02% max: 5.73% x̄: 0.72% x̃: 0.30% HURT stats (abs) min: 2 max: 4 x̄: 3.71 x̃: 4 HURT stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01% 95% mean confidence interval for cycles value: -16.65 -16.13 95% mean confidence interval for cycles %-change: -0.76% -0.66% Cycles are helped. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* nir/flrp: Fix typo on the flrp(±1, b, c) pathIan Romanick2019-05-081-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After Samuel reported the bisect, I was able to find the bug by inspection. Good thing for well-named varibles. :) Unfortunately, this undoes almost all of the benefit of the original patch. Ice Lake total instructions in shared programs: 17183159 -> 17218166 (0.20%) instructions in affected programs: 1308722 -> 1343729 (2.67%) helped: 98 HURT: 4746 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 0.47% max: 2.70% x̄: 0.60% x̃: 0.57% HURT stats (abs) min: 1 max: 691 x̄: 7.40 x̃: 8 HURT stats (rel) min: 0.10% max: 700.00% x̄: 5.82% x̃: 2.83% 95% mean confidence interval for instructions value: 6.82 7.64 95% mean confidence interval for instructions %-change: 5.22% 6.15% Instructions are HURT. total cycles in shared programs: 360705959 -> 360853522 (0.04%) cycles in affected programs: 10754380 -> 10901943 (1.37%) helped: 1594 HURT: 3331 helped stats (abs) min: 1 max: 1896 x̄: 119.81 x̃: 60 helped stats (rel) min: <.01% max: 35.48% x̄: 5.06% x̃: 3.64% HURT stats (abs) min: 1 max: 10208 x̄: 101.63 x̃: 38 HURT stats (rel) min: 0.01% max: 878.95% x̄: 9.01% x̃: 2.78% 95% mean confidence interval for cycles value: 21.11 38.81 95% mean confidence interval for cycles %-change: 3.76% 5.15% Cycles are HURT. total spills in shared programs: 12158 -> 12355 (1.62%) spills in affected programs: 98 -> 295 (201.02%) helped: 1 HURT: 2 total fills in shared programs: 25204 -> 25398 (0.77%) fills in affected programs: 94 -> 288 (206.38%) helped: 0 HURT: 3 LOST: 15 GAINED: 8 Iron Lake total instructions in shared programs: 8121430 -> 8166733 (0.56%) instructions in affected programs: 1148353 -> 1193656 (3.95%) helped: 2 HURT: 4046 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 1.85% max: 1.92% x̄: 1.89% x̃: 1.89% HURT stats (abs) min: 1 max: 43 x̄: 11.20 x̃: 11 HURT stats (rel) min: 0.20% max: 716.67% x̄: 7.40% x̃: 3.87% 95% mean confidence interval for instructions value: 11.02 11.37 95% mean confidence interval for instructions %-change: 6.84% 7.94% Instructions are HURT. total cycles in shared programs: 188376326 -> 188601568 (0.12%) cycles in affected programs: 27416674 -> 27641916 (0.82%) helped: 68 HURT: 3947 helped stats (abs) min: 2 max: 222 x̄: 13.88 x̃: 6 helped stats (rel) min: <.01% max: 1.28% x̄: 0.15% x̃: 0.01% HURT stats (abs) min: 2 max: 670 x̄: 57.31 x̃: 64 HURT stats (rel) min: <.01% max: 1811.11% x̄: 4.11% x̃: 1.09% 95% mean confidence interval for cycles value: 55.01 57.20 95% mean confidence interval for cycles %-change: 2.88% 5.19% Cycles are HURT. LOST: 35 GAINED: 3 GM45 total instructions in shared programs: 4979794 -> 5003551 (0.48%) instructions in affected programs: 635174 -> 658931 (3.74%) helped: 1 HURT: 2142 helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 helped stats (rel) min: 1.85% max: 1.85% x̄: 1.85% x̃: 1.85% HURT stats (abs) min: 1 max: 43 x̄: 11.09 x̃: 11 HURT stats (rel) min: 0.20% max: 716.67% x̄: 7.00% x̃: 3.53% 95% mean confidence interval for instructions value: 10.85 11.33 95% mean confidence interval for instructions %-change: 6.25% 7.74% Instructions are HURT. total cycles in shared programs: 128519586 -> 128654990 (0.11%) cycles in affected programs: 17635304 -> 17770708 (0.77%) helped: 46 HURT: 2088 helped stats (abs) min: 4 max: 220 x̄: 18.13 x̃: 6 helped stats (rel) min: <.01% max: 1.28% x̄: 0.15% x̃: 0.01% HURT stats (abs) min: 2 max: 670 x̄: 65.25 x̃: 66 HURT stats (rel) min: <.01% max: 1464.29% x̄: 4.05% x̃: 0.99% 95% mean confidence interval for cycles value: 61.75 65.15 95% mean confidence interval for cycles %-change: 2.58% 5.34% Cycles are HURT. LOST: 38 GAINED: 38 Fixes: 5b908db604b ("nir/flrp: Lower flrp(±1, b, c) and flrp(a, ±1, c) differently") Reported-by: Samuel Pitoiset <[email protected]> Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]>
* anv: fix use after freeLionel Landwerlin2019-05-081-3/+3
| | | | | | | | Once mem->bo is removed from the cache, it is likely to be freed. Signed-off-by: Lionel Landwerlin <[email protected]> Fixes: b80930a6fea075 ("anv: add support for VK_EXT_memory_budget") Reviewed-by: Eric Engestrom <[email protected]>
* anv: rework queries writes to ensure ordering memory writesLionel Landwerlin2019-05-081-17/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use a mix of MI & PIPE_CONTROL commands to write our queries' data (results & availability). Those commands' memory write order is not guaranteed with regard to their order in the command stream, unless CS stalls are inserted between them. This is problematic for 2 reasons : 1. We copy results from the device using MI commands even though the values are generated from PIPE_CONTROL, meaning we could copy unlanded values into the results and then copy the availability that is inconsistent with the values. 2. We allow the user to poll on the availability values of the query pool from the CPU. If the availability lands in memory before the values then we could return invalid values. This change does 2 things to address this problem : - We use either PIPE_CONTROL or MI commands to write both queries values and availability, so that the ordering of the memory writes guarantees that if availability is visible, results are also visible. - For the occlusion & timestamp queries we apply a CS stall before copying the results on the device, to ensure copying with MI commands see the correct values of previous PIPE_CONTROL writes of availability (required by the Vulkan spec). Signed-off-by: Lionel Landwerlin <[email protected]> Reported-by: Iago Toral Quiroga <[email protected]> Cc: [email protected] Reviewed-by: Jason Ekstrand <[email protected]>
* radv: call constant folding before opt algebraicTimothy Arceri2019-05-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The pattern of calling opt algebraic first seems to have originated in i965. The order in OpenGL drivers generally doesn't matter because the GLSL IR optimisations do constant folding before opt algebraic. However in Vulkan drivers calling opt algebraic first can result in missed constant folding opportunities. vkpipeline-db results (VEGA64): Totals from affected shaders: SGPRS: 3160 -> 3176 (0.51 %) VGPRS: 3588 -> 3580 (-0.22 %) Spilled SGPRs: 52 -> 44 (-15.38 %) Spilled VGPRs: 0 -> 0 (0.00 %) Private memory VGPRs: 0 -> 0 (0.00 %) Scratch size: 12 -> 12 (0.00 %) dwords per thread Code Size: 261812 -> 261036 (-0.30 %) bytes LDS: 7 -> 7 (0.00 %) blocks Max Waves: 346 -> 348 (0.58 %) Wait states: 0 -> 0 (0.00 %) Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
* docs: drop h1 in headerErik Faye-Lund2019-05-08274-279/+274
| | | | | | | | | | | It's generally frowned upon to have more than one H1 per document in HTML4. So let's put the text directly inside the header. This means we can drop the flex-based centering, which makes things a bit easier. We also need to change the padding to rem instead of em, because the em has now changed. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: harmonize headings and titlesErik Faye-Lund2019-05-0812-23/+23
| | | | | | | | | | | | | We're pretty insonsistent in what the headings and titles are, especially compared to what the articles are listed as in the sidebar. Let's harmonize this. There's a notable exception for meson.html, where the sidebar uses a short-hand form that makes sense in the sidebar, but not in the article due to the visible context being different. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: renumber headingsErik Faye-Lund2019-05-0810-83/+87
| | | | | | | | | | | | It's generally frowned upon to have multiple H1 headings in HTML4. So let's make sure each article has a primary heading for the article, and that that heading is the title that is used in the sidebar. While we're at it, let's update the title in the articles to match the title from the sidebar as well. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: give download-article a primary headingErik Faye-Lund2019-05-081-5/+7
| | | | | | | | | | | | It's generally frowned upon to have multiple H1 headings in HTML4. So let's add a primary heading for the article, and source that from the title used in the sidebar. While we're at it, let's update the title in the article to match the title from the sidebar as well. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: use title-casing for all headings in sidebarErik Faye-Lund2019-05-081-10/+10
| | | | | | | | | We generally use title-casing for headings in the sidebar. But not all headings was constently cased like that. Let's make sure this is consistent. Signed-off-by: Erik Faye-Lund <[email protected]> Acked-by: Eric Engestrom <[email protected]>
* docs: spell out "and" in sidebarErik Faye-Lund2019-05-081-3/+3
| | | | | | | | | There's no need to keep this short, we can just spell out "and" here. Besides, a slash kind of implies "or", but these articles are about both of these, not either. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: remove pointless list-entryErik Faye-Lund2019-05-081-1/+0
| | | | | | | | It's quite visible that there's more docs below, we don't need to spell it out for the reader. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: spell out faq in sidebarErik Faye-Lund2019-05-081-1/+1
| | | | | | | | We're not short on space here, so there's little point in abbreviating this. This also matches the heading in the article. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* docs: spell out "and" in sidebarErik Faye-Lund2019-05-081-1/+1
| | | | | | | | | We're not short on space here, so let's just spell out "and" instead of using the ampersand. This is more consistent with the entry above in the sidebar. Signed-off-by: Erik Faye-Lund <[email protected]> Reviewed-by: Eric Engestrom <[email protected]>
* glsl_to_nir: remove unused type_is_int()Timothy Arceri2019-05-081-9/+0
| | | | | | This was missed in e00fa99b08b3. Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]>
* Revert "glx: Fix synthetic error generation in __glXSendError"Timothy Arceri2019-05-081-2/+2
| | | | | | | | | | | This reverts commit e91ee763c378d03883eb88cf0eadd8aa916f7878. This seems to have broken a number of wine games. Lets revert everything for now and try again later. Acked-by: Adam Jackson <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110632 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110590
* radeonsi: add an AMD_TEX_ANISO environment variableTimothy Arceri2019-05-081-0/+4
| | | | | | | This brings it inline with the recently added AMD_DEBUG. Reviewed-by: Marek Olšák <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109619
* i965: leave the top 4Gb of the high heap VMA unusedKenneth Graunke2019-05-071-1/+5
| | | | | | | | This ports commit 9e7b0988d6e98690eb8902e477b51713a6ef9cae from anv to i965. Thanks to Lionel for noticing that it was missing! Fixes: 01058a55229 i965: Add virtual memory allocator infrastructure to brw_bufmgr. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Force VMA alignment to be a multiple of the page size.Kenneth Graunke2019-05-071-0/+2
| | | | | | | This should happen regardless, but let's be paranoid. Fixes: 01058a55229 i965: Add virtual memory allocator infrastructure to brw_bufmgr. Reviewed-by: Jason Ekstrand <[email protected]>
* i965: Fix BRW_MEMZONE_LOW_4G heap size.Kenneth Graunke2019-05-071-1/+4
| | | | | | | | | | The STATE_BASE_ADDRESS "Size" fields can only hold 0xfffff in pages, and 0xfffff * 4096 = 4294963200, which is 1 page shy of 4GB. So we can't use the top page. Fixes: 01058a55229 i965: Add virtual memory allocator infrastructure to brw_bufmgr. Reviewed-by: Jason Ekstrand <[email protected]>
* intel/compiler: Unset flag reg when FB write is not predicatedMatt Turner2019-05-071-0/+1
| | | | | | | | | | | In the FS IR we pretend that the instruction is predicated with (+f0.1) just for flag dependency tracking purposes. Since the instruction doesn't support predication before Haswell, we unset the predicate so we should also unset the flag register so that we can round-trip the disassembly. Reviewed-by: Sagar Ghuge <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]>
* intel/disasm: Disassemble immediate value properly for dimSagar Ghuge2019-05-071-3/+12
| | | | | | | | | | On haswell, for dim instruction we encode immediate float value operand into double float, v2: Fix comment (Matt Turner) Signed-off-by: Sagar Ghuge <[email protected]> Reviewed-by: Matt Turner <[email protected]>
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