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* mesa: fix GLSL program objects with more than 16 samplers combinedMarek Olšák2013-05-289-113/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | The problem is the sampler units are allocated from the same pool for all shader stages, so if a vertex shader uses 12 samplers (0..11), the fragment shader samplers start at index 12, leaving only 4 sampler units for the fragment shader. The main cause is probably the fact that samplers (texture unit -> sampler unit mapping, etc.) are tracked globally for an entire program object. This commit adapts the GLSL linker and core Mesa such that the sampler units are assigned to sampler uniforms for each shader stage separately (if a sampler uniform is used in all shader stages, it may occupy a different sampler unit in each, and vice versa, an i-th sampler unit may refer to a different sampler uniform in each shader stage), and the sampler-specific variables are moved from gl_shader_program to gl_shader. This doesn't require any driver changes, and it fixes piglit/max-samplers for gallium and classic swrast. It also works with any number of shader stages. v2: - converted tabs to spaces - added an assertion to _mesa_get_sampler_uniform_value Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* swrast: increase array size of TextureSampleMarek Olšák2013-05-282-4/+4
| | | | | | | | to match the size of ctx->Texture.Unit, and it will also fix piglit/max-samplers with the following commit. Reviewed-by: Ian Romanick <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* mesa: declare UniformBufferBindings as an array with a static sizeMarek Olšák2013-05-284-14/+9
| | | | | | | | Some Gallium drivers were crashing, because the array was not large enough. v2: clamp the per-shader maximum in st/mesa, then sum them all up NOTE: This is a candidate for the stable branches.
* radeonsi: Enable GLSL 1.30Michel Dänzer2013-05-281-1/+1
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* radeonsi: Handle TGSI TXQ opcodeMichel Dänzer2013-05-282-3/+33
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* radeonsi: Add support for TGSI TXF opcodeMichel Dänzer2013-05-282-14/+51
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* radeonsi: Use tgsi_util_get_texture_coord_dim()Michel Dänzer2013-05-281-25/+7
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* radeonsi: Handle TGSI_SEMANTIC_CLIPDISTMichel Dänzer2013-05-281-4/+17
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* radeonsi: Make border colour state handling safe for integer texturesMichel Dänzer2013-05-282-20/+27
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* radeonsi: Fix hardware state for dual source blendingMichel Dänzer2013-05-284-6/+17
| | | | | Set up CB_SHADER_MASK register according to pixel shader exports, and enable some minimal state for colour buffer 1 in case dual source blending is used.
* r600g/sb: handle more cases for folding in gvn passVadim Girlin2013-05-282-28/+118
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* st/vdpau: destroy handle table only when it's emptyChristian König2013-05-271-1/+1
| | | | Signed-off-by: Christian König <[email protected]>
* st/vdpau: remove vlCreateHTAB from surface functionsChristian König2013-05-271-9/+0
| | | | Signed-off-by: Christian König <[email protected]>
* st/vdpau: invalidate the handles on destructionChristian König2013-05-273-0/+4
| | | | | | Fixes a problem with xbmc when switching channels. Signed-off-by: Christian König <[email protected]>
* r600g/sb: improve folding for SETccVadim Girlin2013-05-271-8/+98
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: optimize CNDcc instructionsVadim Girlin2013-05-273-1/+113
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: improve optimization of conditional instructionsVadim Girlin2013-05-276-21/+96
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* ilo: enable multiple constant buffersChia-I Wu2013-05-271-1/+1
| | | | This effectively enables uniform buffer object support.
* ilo: add support for indirect access of CONST in FSChia-I Wu2013-05-272-2/+99
| | | | | Unlike other register files, CONST is read with a message and indirect access is easier to implement.
* ilo: add support for TBOs on GEN6Chia-I Wu2013-05-271-8/+26
| | | | This hunk was missing in the last commit.
* ilo: advertise supports for pure integer formatsChia-I Wu2013-05-271-2/+3
| | | | For pure integer formats, no filtering nor blending is needed.
* ilo: add support for texture buffer objectsChia-I Wu2013-05-272-10/+32
| | | | | Take care of sampler views that have buffers as the underlying resources. Update caps related to TBOs.
* tgsi: add buffer texture to tgsi_util_get_texture_coord_dim()Chia-I Wu2013-05-272-0/+3
| | | | | | | | TGSI_TEXTURE_BUFFER is one-dimensional. Assert that exec_tex() is never called with TGSI_TEXTURE_BUFFER. Signed-off-by: Chia-I Wu <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* r600g/sb: improve handling of KILL instructionsVadim Girlin2013-05-273-89/+139
| | | | | | | This patch improves handling of unconditional KILL instructions inside the conditional blocks, uncovering more opportunities for if-conversion. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix peephole optimization for PRED_SETEVadim Girlin2013-05-271-1/+1
| | | | | | | Fixes incorrect condition that prevented optimization for PRED_SETE/PRED_SETE_INT. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix scheduling of PRED_SET instructionsVadim Girlin2013-05-272-2/+18
| | | | | | | | | | | | | | PRED_SET instructions that update exec mask should be scheduled immediately prior to the "if-then-else" block, because any instruction that is inserted after alu clause with PRED_SET and before conditional block is also conditionally executed by hw (exec mask is already updated at that moment). Propbably it's better to make PRED_SET a part of conditional "if-then-else" block in the IR to handle this more cleanly, but for now this temporary solution should prevent the problem. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix handling of preloaded inputs for compute shadersVadim Girlin2013-05-251-0/+4
| | | | | | | | | | For compute shaders we need to let the backend know that GPRs 0 and 1 are preloaded with some compute-specific input values, otherwise any use of these regs without previous definition is considered as undefined value and usually is simply replaced with 0. Signed-off-by: Vadim Girlin <[email protected]>
* xlib: add null ctx check in glXDestroyContext()Brian Paul2013-05-241-10/+12
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934 NOTE: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* st/glx: add null ctx check in glXDestroyContext()Brian Paul2013-05-241-10/+12
| | | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64934 NOTE: This is a candidate for the stable branches. Reviewed-by: Jose Fonseca <[email protected]>
* st/mesa: add switch cases for new IR enums to silence warningsBrian Paul2013-05-241-0/+2
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* st/glx/xlib: assorted whitespace, comment fixesBrian Paul2013-05-241-8/+17
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* r600g/sb: fix incorrect assertVadim Girlin2013-05-241-1/+1
| | | | Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: relax some restrictions for FETCH instructionsVadim Girlin2013-05-241-9/+8
| | | | | | | | This allows GVN rewrite pass to propagate non-const (register) values to FETCH source operands, helping to eliminate unnecessary copies in some cases. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: relax register allocation for compute shadersVadim Girlin2013-05-242-2/+16
| | | | | | | | | | | | | | We have to assume that all GPRs in compute shader can be indirectly addressed because LLVM backend doesn't provide any indirect array info. That's why for compute shaders GPR array is created that covers all used GPRs (0..r600_bytecode::ngpr-1), but this seriously restricts register allocation in sb. This patch checks for actual use of indirect access in the shader and if it's not used then GPR array is not created, so that regalloc is not unnecessarily restricted. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix gpr array handling for compute shadersVadim Girlin2013-05-241-1/+1
| | | | | | Fixes segfault with bfgminer and R600_DEBUG=sbcl. Signed-off-by: Vadim Girlin <[email protected]>
* r600g/sb: fix buffer overflow in sb_ostreamVadim Girlin2013-05-241-1/+1
| | | | | | Fixes segfault during bytecode dump with bfgminer kernel Signed-off-by: Vadim Girlin <[email protected]>
* r600g/compute: Use common transfer_{map,unmap} functions for global resourcesTom Stellard2013-05-231-44/+24
| | | | Reviewed-by: Marek Olšák <[email protected]>
* r600g/compute: Use common transfer_{map,unmap} functions for kernel inputsTom Stellard2013-05-231-4/+11
| | | | Reviewed-by: Marek Olšák <[email protected]>
* i965: Go back to using the kernel SOL reset feature.Kenneth Graunke2013-05-233-8/+7
| | | | | | | | | | | | | | | It turns out the MI_LOAD_REGISTER_IMM approach doesn't work on Haswell, and regressed essentially all the transform feedback Piglit tests. This morally reverts eaa6fbe6d54dc99efac4ab8e800edef65ce8220d. However, the code is still simpler than it was. On BeginTransformFeedback, we simply flush the batch and set the SOL reset flag so that the next batch will start with zeroed offsets. There's still no software counting. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64887 Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Paul Berry <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* freedreno: scissor fixRob Clark2013-05-231-0/+11
| | | | | | | Don't assume the state-tracker will set the scissor after the framebuffer state is changed. Signed-off-by: Rob Clark <[email protected]>
* freedreno: implement pipe->resource_copy_region()Rob Clark2013-05-231-8/+43
| | | | Signed-off-by: Rob Clark <[email protected]>
* glsl linker: compare interface blocks during interstage linkingKenneth Graunke2013-05-233-0/+49
| | | | | | | | | | | | Verify that interface blocks match when linking separate shader stages into a program. Fixes piglit glsl-1.50 tests: * linker/interface-blocks-vs-fs-member-count-mismatch.shader_test * linker/interface-blocks-vs-fs-member-order-mismatch.shader_test Signed-off-by: Kenneth Graunke <[email protected]> Signed-off-by: Jordan Justen <[email protected]>
* glsl linker: compare interface blocks during intrastage linkingJordan Justen2013-05-234-0/+82
| | | | | | | | | | | | | | | | Verify that interface blocks match when combining compilation units at the same stage. (For example, when merging all vertex shaders.) Fixes piglit glsl-1.50 test: * linker/interface-blocks-multiple-vs-member-count-mismatch.shader_test v5 (Ken): Rename to link_interface_blocks.cpp and drop the separate .h file for consistency with other linker code. Remove "ok" variable. Fold cross_validate_interface_blocks into its caller. Signed-off-by: Jordan Justen <[email protected]> Signed-off-by: Kenneth Graunke <[email protected]>
* glsl linker: support arrays of interface block instancesJordan Justen2013-05-231-11/+50
| | | | | | | | | | | | | | | With this change we now support interface block arrays. For example, cases like this: out block_name { float f; } block_instance[2]; This allows Mesa to pass the piglit glsl-1.50 test: * execution/interface-blocks-complex-vs-fs.shader_test Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl link_varyings: link interface blocks using the block nameJordan Justen2013-05-231-4/+29
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl linker: remove interface block instance namesJordan Justen2013-05-234-0/+207
| | | | | | | | Convert interface blocks with instance names into flat interface blocks without an instance name. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl ast_to_hir: support in/out for interface blocksJordan Justen2013-05-231-6/+22
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl ast_to_hir: reject row/column_major for in/out interface blocksJordan Justen2013-05-231-1/+5
| | | | | Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl ast_to_hir: move uniform block symbols to interface blocks namespaceJordan Justen2013-05-231-1/+1
| | | | | | | Uniform/interface blocks are a separate namespace from types. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
* glsl_symbol_table: add interface block namespacesJordan Justen2013-05-232-3/+85
| | | | | | | | For interface blocks, there are three separate namespaces for uniform, input and output blocks. Signed-off-by: Jordan Justen <[email protected]> Reviewed-by: Kenneth Graunke <[email protected]>
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