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* i965/blorp: Move the guts of brw_blorp_exec into genX_blorp_exec.cJason Ekstrand2016-08-292-66/+66
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Pull the guts of blorp_exec into a driver-agnostic headerJason Ekstrand2016-08-293-1101/+1180
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/exec: Refactor to use a new blorp_batch structJason Ekstrand2016-08-293-148/+195
| | | | | | | | | This gets rid of brw_context throughout the core of the state setup code. Instead, it is replaced with blorp_batch which contains a pointer to the blorp_context and a void* that the driver can use for its own blorp data. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add a helper for allocating binding tables and surface statesJason Ekstrand2016-08-291-22/+42
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use BT_INDEX enums for setting up the binding tableJason Ekstrand2016-08-291-2/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Shorten binding table index enum namesJason Ekstrand2016-08-292-6/+6
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/genX: Add a blorp_surface_reloc helperJason Ekstrand2016-08-291-17/+21
| | | | | | | | | | | Previously, we passed the buffer address (as per the latest offset from the kernel) to ISL to use when it filled out the surface state. We then called drm_intel_bo_emit_reloc() to add the relocation to the list. The newly added blorp_surface_reloc helper adds the relocation to the list and then writes the buffer address directly into the surface state. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use blorp_address in brw_blorp_surface instead of bo+offsetJason Ekstrand2016-08-296-68/+64
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Pull emit_surface_state into genX_blorp_exec.cJason Ekstrand2016-08-293-86/+80
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Add driver mocs settings to the contextJason Ekstrand2016-08-294-18/+39
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/genX: Move emit_urb_config into another helperJason Ekstrand2016-08-291-13/+17
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Use gen6_upload_urbJason Ekstrand2016-08-291-4/+2
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/gen6: Refactor gen6_upload_urbJason Ekstrand2016-08-292-24/+35
| | | | | | | This splits it into two functions very similar to gen7_upload_urb. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/genX: Pull emit_3dstate_multisample into a helperJason Ekstrand2016-08-291-5/+11
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp/genX: Add helpers for allocating various bits of stateJason Ekstrand2016-08-291-32/+53
| | | | | | | | This pulls most of the brw-specific bits into helpers with generic names. Later, those will become the driver hooks for generic code. Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* i965/blorp: Expose the shader cache through function pointersJason Ekstrand2016-08-294-18/+47
| | | | | | | | | | | | | | | This sanitizes blorp's access to the i965 driver's shader cache by patching it through the blorp_context. When we start using blorp in Vulkan, we will simply have to implement such a caching interface in the Vulkan driver. Note: In my first attempt at this, I simplified it down to a single upload_shader entrypoint and implemented the caching inside of blorp. This doesn't work, however, because the i965 driver will, on occation, dump its entire cache and start over. When this happens, blorp needs to be able to recompile its shaders and re-upload them. It's easiest to just expose the caching interface. Signed-off-by: Jason Ekstrand <[email protected]>
* i965/blorp: Add a blorp_context struct and init/finish funcsJason Ekstrand2016-08-296-0/+42
| | | | | Signed-off-by: Jason Ekstrand <[email protected]> Reviewed-by: Topi Pohjolainen <[email protected]>
* android: intel: Flatten the makefile structureMauro Rossi2016-08-294-48/+75
| | | | | | | | | | | Android porting of commit bebc1a1 "intel: Flatten the makefile structure" Automake approach was followed, by moving makefiles a level up, naming them Android.genxml.mk and Android.isl.mk, performing the necessary adjustments to the paths, adding src/intel/Android.mk and fixing mesa top level makefile. Acked-by: Jason Ekstrand <[email protected]>
* clover: Use device cap to query pointer size instead of hardcoded 32bitsJan Vesely2016-08-293-1/+8
| | | | | | Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97513 Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Francisco Jerez <[email protected]>
* gallium: add cap to export device pointer sizeJan Vesely2016-08-297-0/+22
| | | | | | | | | v2: document the new cap v3: fix 80 char limit in screen.rst Signed-off-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Acked-by: Ilia Mirkin <[email protected]>
* svga: s/unsigned/enum pipe_shader_type/Brian Paul2016-08-2911-22/+24
| | | | Reviewed-by: Charmaine Lee <[email protected]>
* i965/hsw: Enable ARB_ES3_1_compatibility extensionJordan Justen2016-08-292-2/+3
| | | | | | Signed-off-by: Jordan Justen <[email protected]> Acked-by: Kenneth Graunke <[email protected]> Reviewed-by: Samuel Iglesias Gonsálvez <[email protected]>
* r600g: Clean up defined magic numbers for TGSI opcodesRhys Kidd2016-08-292-7/+8
| | | | | | | | | | | | Small code clean up that removes magic numbers where a TGSI opcode has been defined. No functional change expected as each opcode is unsupported on the respective hardware. Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: James Harvey <[email protected]>
* r600g: Avoid duplicated initialization of TGSI_OPCODE_DFMARhys Kidd2016-08-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As reported by Clang, TGSI_OPCODE_DFMA (defined magic number 118) is currently initialized twice for Cayman and Evergreen. When Jan Vesely added double precision FMA opcode it did make sense to locate it immediately after TGSI_OPCODE_DMAD, although this is out of order. This change cleans up the prior magic number definition and ensures any later reordering of this struct will not create problems. Prior change was: commit 015e2e0fce3eea7884f8df275c2fadc35143a324 Author: Jan Vesely <[email protected]> Date: Sat Jul 2 16:14:54 2016 -0400 r600g: Add double precision FMA ops Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96782 Fixes: 54c4d525da7c7fc1e103d7a3e6db015abb132d5d ("r600g: Enable FMA on chips that support it") Signed-off-by: Jan Vesely <[email protected]> Tested-by: James Harvey <[email protected]> Signed-off-by: Marek Olšák <[email protected]> Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Jan Vesely <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Tested-by: James Harvey <[email protected]>
* i915g: Fix typo in i915_translate_instruction()Rhys Kidd2016-08-291-1/+1
| | | | | | | | | | | Noticed this error in a debug message whilst reviewing https://bugs.freedesktop.org/show_bug.cgi?id=97477 This patch doesn't go towards fixing that bug, but at least may clarify future debug output. Signed-off-by: Rhys Kidd <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
* vc4: Handle discards while in control flow.Eric Anholt2016-08-292-6/+28
| | | | | I missed this while adding loop support because the discard test inside a loop was crashing before, anyway. Fixes piglit glsl-fs-discard-04.
* vc4: Mark when we add discards while lowering blend state.Eric Anholt2016-08-291-0/+1
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* nir: Update shader info when adding discardsEric Anholt2016-08-292-0/+4
| | | | | | | vc4 is about to start using the shader info field to set up discard handling. Reviewed-by: Jason Ekstrand <[email protected]>
* swr: [rasterier core] fix GetRasterizerFunc selectionTim Rowley2016-08-292-4/+4
| | | | | | | Only rasterize scissor edges if one or more scissor/viewport rects are not hottile aligned. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] whitespace cleanupTim Rowley2016-08-291-3/+1
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer jitter] reimplement SCATTERPSTim Rowley2016-08-292-16/+100
| | | | | | | Implement SCATTERPS as a dynamic loop based on mask set bits instead of a static compile time loop. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] upper left rule for scissorsTim Rowley2016-08-292-4/+12
| | | | | | Fixes upper left rule for scissors and viewport/scissor macrotile alignment. Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer scripts] undef DEFINE_KNOB after usageTim Rowley2016-08-291-0/+2
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] minor cleanup to thread initializationTim Rowley2016-08-293-13/+12
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] remove KNOB_MAX_THREADSTim Rowley2016-08-296-51/+77
| | | | | | Use dynamic memory allocation for per-thread data Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] track guardbands per viewport rectTim Rowley2016-08-293-18/+26
| | | | Signed-off-by: Tim Rowley <[email protected]>
* swr: [rasterizer core] per-primitive viewports/scissorsTim Rowley2016-08-297-71/+214
| | | | | | | | - use per-primitive viewports throughout the pipeline. - track whether all available scissor rects are tile aligned. Causes failures, so not taken into account when choosing rasterizer yet. Signed-off-by: Tim Rowley <[email protected]>
* radeonsi: Don't use global variables for tess ldsTom Stellard2016-08-291-9/+6
| | | | | | | | | We were allocating global variables for the maximum LDS size which made the compiler think we were using all of LDS, which isn't the case. Reviewed-By: Edward O'Callaghan <[email protected]> Reviewed-by: Marek Olšák <[email protected]>
* softpipe: (trivial) honor render_condition_enabled for clear_rt/clear_dsRoland Scheidegger2016-08-291-2/+2
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* llvmpipe: (trivial) honor render_condition_enabled for clear_rt/clear_dsRoland Scheidegger2016-08-291-2/+2
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* gallium: Use enum pipe_shader_type in set_shader_images()Kai Wasserbäch2016-08-2910-10/+16
| | | | | Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: Use enum pipe_shader_type in set_shader_buffers()Kai Wasserbäch2016-08-297-9/+12
| | | | | Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: Use enum pipe_shader_type in set_sampler_views()Kai Wasserbäch2016-08-2934-42/+54
| | | | | Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium: Use enum pipe_shader_type in bind_sampler_states() (v2)Kai Wasserbäch2016-08-2928-38/+63
| | | | | | | | | | | v1 → v2: - Fixed indentation (noted by Brian Paul) - Removed second assert from nouveau's switch statements (suggested by Brian Paul) Signed-off-by: Kai Wasserbäch <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Brian Paul <[email protected]>
* gallium/radeon: clear dirty_level_mask when discarding CMASKMarek Olšák2016-08-291-0/+1
| | | | | | This fixes: GL45-CTS.texture_barrier.* Tested-by: Michel Dänzer <[email protected]>
* tgsi/scan: remember sampler view typesMarek Olšák2016-08-292-0/+5
| | | | Reviewed-by: Brian Paul <[email protected]>
* st/vdpau: use temporary buffers while applying filtersNayan Deshmukh2016-08-291-18/+57
| | | | | | | | | | | Use temporary buffers so that we don't read and write to the same surface at the same time. We don't need to use linear layout now. v2: rebase the patch against reverted change Signed-off-by: Nayan Deshmukh <[email protected]> Reviewed-by: Christian König <[email protected]>
* st/vdpau: Revert "change the order in which filters are applied(v3)"Christian König2016-08-291-18/+10
| | | | | | | | | | This reverts commit 09dff7ae2e179d5a3490481762c6bd3d50430c9f. Turned out this can cause some artifacts in the output. Let's revert it for now until we have sorted out all issues. Signed-off-by: Christian König <[email protected]> Reviewed-by: Nayan Deshmukh <[email protected]>
* i965/vec4: remove the generator hack for dual instanced GSIago Toral Quiroga2016-08-291-31/+0
| | | | | | | | | | | | | | | | | | | | | | This hack was introduced in commit 03ac2c7223f7645e3: i965/gs: Fix up gl_PointSize input swizzling for DUAL_INSTANCED gs Specifically to fixup the code we emitted to deal with gl_PointSize inputs in dual instance mode, where we were emitting a MOV to copy the point size from .w (where the hardware delivers it) to .x (because code will expect this to be a float). This meant that we were emitting a MOV to an ATTR destination that could have a width of 4 (in dual instanced mode) so it was necessary to fix the execution size and regioning of the instruction. Fortunately, Ken fixed this in 67c5d00273ca2: i965/vec4/gs: Stop munging the ATTR containing gl_PointSize. by using a WWWW swizzle instead of a MOV, and as the commit log in that patch states, we no longer emit instructions with ATTR destinations, so that makes the fixup code in the generator unnecessary. Reviewed-by: Francisco Jerez <[email protected]>
* glsl: initialise pointer to NULLTimothy Arceri2016-08-291-1/+1
| | | | | | Fixes uninitialised warning and covery defect. Reviewed-by: Kenneth Graunke <[email protected]>
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