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* lima: print gp uniforms if gp debug is enabledVasily Khoruzhick2020-03-111-0/+13
| | | | | | | | Since we keep other constants there as well it's useful for reading disassembly. Reviewed-by: Andreas Baierl <[email protected]> Signed-off-by: Vasily Khoruzhick <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4110>
* gitlab-ci: add rules:changes for RADVSamuel Pitoiset2020-03-112-0/+12
| | | | | | | | | | Including mesa_core_file_list is probably not the best but it's better than nothing. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4117> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4117>
* gallium: hud_context: Fix scalar initializer warning.John Stultz2020-03-111-1/+3
| | | | | | | | | | | | | | | | | When trying to build mesa/master under AOSP, I've run into the following error: external/mesa3d/src/gallium/auxiliary/hud/hud_context.c:1821:31: error: braces around scalar initializer [-Werror,-Wbraced-scalar-init] struct sigaction action = {{0}}; ^~~ 1 error generated. This patch addresses this by switching to using memset instead of using an initializer. Signed-off-by: John Stultz <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
* panfrost: Move pan_afbc.c file to the the right Makefile.source fileJohn Stultz2020-03-112-1/+1
| | | | | | | | | | It seems pan_afbc.c was added to the wrong Makefile.sources file. So fix this, so we don't run into build issues with mesa/master trying to build under AOSP. Signed-off-by: John Stultz <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
* freedreno: Add ir3_cf.c and ir3_delay.c to Makefile.sourcesJohn Stultz2020-03-111-0/+2
| | | | | | | | | This patch adds missing ir3_cf.c and ir3_delay.c files to the Makefile.sources file to address build issues seen when trying to build mesa/master on AOSP Signed-off-by: John Stultz <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4141>
* gallium/cso_context: remove cso_delete_xxx_shader helpers to fix the live cacheMarek Olšák2020-03-1010-106/+74
| | | | | | | | | | | | | | | | | | With the live shader cache, equivalent shaders can be backed by the same CSO. This breaks the logic that identifies whether the shader being deleted is bound. For example, having shaders A and B, you can bind shader A and delete shader B. Deleting shader B will unbind shader A if they are equivalent. Pierre-Eric figured out the root cause for this issue. Fixes: 0db74f479b9 - radeonsi: use the live shader cache Closes: #2596 Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4078> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4078>
* vulkan/wsi: fix cleanup when dup() failsEric Engestrom2020-03-101-1/+1
| | | | | | | | Fixes: f5433e4d6ce247b86dae ("vulkan/wsi: Add modifiers support to wsi_create_native_image") Signed-off-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4137> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4137>
* Revert "gallium: make handles of set_global_binding 64 bit"Karol Herbst2020-03-1013-27/+42
| | | This reverts commit e1ffb72a05f9b50ee47767aaadbab3e47896ee14
* gallium: make handles of set_global_binding 64 bitKarol Herbst2020-03-1013-42/+27
| | | | | | | | | | needed by CL Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4072> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4072>
* pan/bi: Implement comparison opcodes via BI_CMPAlyssa Rosenzweig2020-03-101-0/+41
| | | | | | | | | Pretty straightforward for the moment. Ideally these would be fused into csel/branches but that will come a bit later. Signed-off-by: Alyssa Rosenzweig <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Print source types unconditionallyAlyssa Rosenzweig2020-03-101-8/+3
| | | | | | | We track them all now, let's use them. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Specify comparison op for BI_CMPAlyssa Rosenzweig2020-03-102-9/+12
| | | | | | | ...and adjust printing so we can use it as an op name. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Lower b2f to bcselAlyssa Rosenzweig2020-03-101-0/+2
| | | | | | | | | Since we can get a zero for free and a one inlined into the constant, the obvious turns out to be efficient (while allowing flexibility for boolean size). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Implement nir_op_bcselAlyssa Rosenzweig2020-03-101-0/+3
| | | | | | | No condition fusing yet. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Import algebraic pass from midgardAlyssa Rosenzweig2020-03-104-1/+116
| | | | | | | We'll need some of these at least. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Add isub opAlyssa Rosenzweig2020-03-104-0/+5
| | | | | | | | Can't be a regular ADD since there's no negate modifier for integers (it's a different opcode entirely). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Disable lower_subAlyssa Rosenzweig2020-03-102-1/+4
| | | | | | | | For float, fixing up the modifier ourselves is easy. For int, we have a dedicated isub instruction anyway. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Implement fabs, fneg as fmov with modsAlyssa Rosenzweig2020-03-101-0/+8
| | | | | | | Fusing will come later with the appropriate NIR support. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Handle special ops in NIR->BIRAlyssa Rosenzweig2020-03-101-0/+21
| | | | | | | | | | | Only on supported GPUs at the moment; for older Bifrost that don't support these, I'm not sure yet where the right place to do the lowering is. NIR algebraic rules would be "nice" but probably impractical -- but it wouldn't be hard to do it directly in BIR (as a lowering pass or alternative implementation). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Add BI_SPECIAL_* enumAlyssa Rosenzweig2020-03-102-0/+30
| | | | | | | To disambiguate the different special ops from each other. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Add a bunch of ALU opsAlyssa Rosenzweig2020-03-101-4/+47
| | | | | | | | | These are all regular ALU ops found in GLES2 which makes them particularly nice targets at the moment. Just translate straight to our IR. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Implement fsat as mov.satAlyssa Rosenzweig2020-03-101-0/+4
| | | | | | | | Soon we'll have a NIR support to handle this the Right Way along with pos and sat_signed support, but we'll always need the fallback anyway. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Allow inlining constantsAlyssa Rosenzweig2020-03-101-3/+23
| | | | | | | | This will allow us to optimize out the constant moves (although that will require a DCE pass which has yet to be written). Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Add initial handling of ALU opsAlyssa Rosenzweig2020-03-101-1/+65
| | | | | | | | | We do the bare minimum translation, just enough for fmov/fadd/fmul right now with no modifiers / inlined constants / etc. The rest is to come! But hopefully I got bitsize handling right this time around. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Lower vec* to writemasks in NIRAlyssa Rosenzweig2020-03-101-0/+8
| | | | | | | I was hoping not to tread down this path but it seems inevitable now. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Remove bi_loadAlyssa Rosenzweig2020-03-103-97/+38
| | | | | | | This is now made redundant with writemasks, so let's regularize the IR. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Introduce writemasksAlyssa Rosenzweig2020-03-103-5/+45
| | | | | | | | I feel so dirty. But this will let the IR be a lot more flexible seeing as we really are vector in a certain sense (I/O, small types) Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* pan/bi: Generalize swizzles to avoid extractsAlyssa Rosenzweig2020-03-103-18/+19
| | | | | | | | | | We'd really rather not emit extracts. We are approaching on a vector IR anyway which is annoying but really necessary to handle I/O and fp16 correctly. So let's just go all the way and deal with swizzles and masks within reason; it'll still be somewhat saner in the long-term. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* panfrost: Move mir_to_bytemask to common codeAlyssa Rosenzweig2020-03-1010-49/+146
| | | | | | | | ...also so we can start sharing code properly between the panfrost compilers. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4139>
* freedreno/fdperf: set localeRob Clark2020-03-101-0/+3
| | | | | | | | | Set local to get numbers printed w/ commas.. much easier to read that way. Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119>
* freedreno/computerator: add performance counter supportRob Clark2020-03-104-1/+236
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4119>
* vulkan/wsi: Return an error if dup() failsJason Ekstrand2020-03-101-0/+1
| | | | | | | Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135>
* vulkan/wsi: Don't leak the FD when GetImageDrmFormatModifierProperties failsJason Ekstrand2020-03-101-1/+3
| | | | | | Cc: [email protected] Reviewed-by: Lionel Landwerlin <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4135>
* freedreno/ir3: try to avoid syncsRob Clark2020-03-101-1/+55
| | | | | | | | | | Update postsched to be better aware of where costly (ss) syncs would result. Sometimes it is better to allow a nop or two, to avoid a sync quickly after an SFU. Signed-off-by: Rob Clark <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno/ir3: round-robin RARob Clark2020-03-101-4/+163
| | | | | | | | | | | | | | | | In the second (scalar pass) use the information about # of registers used in the first pass as the target max, and round-robin within that range. This generally gives the post-RA sched pass more opportunities to re-order instructions to remove nop's. Also, we can be a bit clever when assigning dest registers for SFU instructions, by picking the register used for it's src (if available and already assigned). This avoids some (ss) syncs caused by write after read hazards. (Ie. the SFU instruction will read it's own src before writing dest.) Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno/ir3: track register usage in first RA passRob Clark2020-03-101-0/+41
| | | | | | | | We'll use the feedback from the first pass to select a target register usage in the second pass. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno/ir3: fix has_latency_to_hideRob Clark2020-03-101-1/+8
| | | | | | | | Also count tex-prefetch instructions. And only let the no-latency rule kick in for frag shaders. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno/ir3: split out has_latency_to_hide()Rob Clark2020-03-102-25/+25
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* util/ra: move NO_REG to headerRob Clark2020-03-102-2/+4
| | | | | | | | | In the select_reg callback, I want to be able to determine if a given node is already assigned, and if so what physical register has been assigned. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* util/ra: spiff out select_reg_callbackRob Clark2020-03-104-11/+26
| | | | | | | | | | | | Add a parameter so the callback can know which node it is selecting a register for. And remove the graph parameter, as it is unused by existing users, and somewhat unnecessary (ie. the callback data could be used instead). And add a comment so $future_me remembers how this works. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno: fix FD_MESA_DEBUG=inorderRob Clark2020-03-101-1/+1
| | | | | | Fixes: 2c07e03b792 ("freedreno: allow ctx->batch to be NULL") Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno/ir3: add simplified stall estimationRob Clark2020-03-103-2/+16
| | | | | | | | | Doesn't take into account stalls that result from a register written in a different block, etc. But this should be more useful than just using number of (ss)'s by trying to estimate how costly a given sync is. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno/ir3: remove extra nops inserted in schedulerRob Clark2020-03-102-25/+0
| | | | | | | | | They were inserting a nop between back to back SFU instrucions. But that doesn't actually appear to be required. And they get stripped out later anyways before legalize. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno/computerator: add hrsq/hlog2/hexp2Rob Clark2020-03-102-0/+9
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* freedreno/ir3: also lower lowp frag outputsRob Clark2020-03-101-1/+2
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* nir/print: show variable precisionRob Clark2020-03-101-0/+10
| | | | | Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4071>
* intel/tools: Fix compilation with UBSanDanylo Piliaiev2020-03-101-1/+1
| | | | | | | | | | | | Compilation failed with several similar errors: ../src/intel/tools/aub_read.c:322:4: error: case label does not reduce to an integer constant 322 | case MAKE_HEADER(TYPE_AUB, OPCODE_AUB, SUBOPCODE_HEADER): Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4132> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4132>
* i965: Use gl_vertex_format in brw_vertex_element.Mathias Fröhlich2020-03-103-15/+13
| | | | | | | | | | | State upload needs to cope with the vertex format rather than with the full attribute data. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
* i965: Make use of the vertex format functions in i965.Mathias Fröhlich2020-03-101-6/+4
| | | | | | | | | v2: Style fixes. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
* mesa: Provide gl_vertex_format accessors.Mathias Fröhlich2020-03-101-0/+21
| | | | | | | | | | | | | Provide the same set of VAO and current value gl_vertex_format accessor functions like we have for the gl_array_attributes. For most purpose the vertex format is what we need. v2: Style fixes. Reviewed-by: Matt Turner <[email protected]> Reviewed-by: Ian Romanick <[email protected]> Signed-off-by: Mathias Fröhlich <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/308>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 20:20:33 +0000