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* llvmpipo/nir: free compute shader NIRDave Airlie2020-05-061-0/+2
| | | | | | | | | I forgot this in the last round. Fixes: 18f896e55d96 (llvmpipe: add initial nir support) Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4899>
* draw/tess: free tessellation control shader i/o memory.Dave Airlie2020-05-061-0/+3
| | | | | | | Fixes: 0d02a7b8ca79 (draw: add main tessellation code) Reviewed-by: Roland Scheidegger <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4899>
* nir: add missing group_memory_barrier handlingRhys Perry2020-05-052-0/+2
| | | | | | | | | | | | | | | Totals from 2 (0.00% of 127638) affected shaders: VGPRs: 164 -> 168 (+2.44%) CodeSize: 18420 -> 18756 (+1.82%) Instrs: 3658 -> 3700 (+1.15%) Cycles: 82912 -> 83080 (+0.20%) VMEM: 70 -> 69 (-1.43%) PreVGPRs: 155 -> 168 (+8.39%) Signed-off-by: Rhys Perry <[email protected]> Reviewed-by: Caio Marcelo de Oliveira Filho <[email protected]> CC: <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4889>
* freedreno/ir3: Disable sin/cos range reduction for mediump.Eric Anholt2020-05-051-2/+2
| | | | | | | | | | robclark noted that the blob wasn't doing range reduction in the mediump case, and I confirmed it on dEQP-GLES3.functional.shaders.operator.angle_and_trigonometry.sin.mediump_float_fragment vs dEQP-GLES3.functional.shaders.operator.angle_and_trigonometry.sin.highp_float_fragment. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4893>
* st/nine: Set correctly blend max_rtAxel Davy2020-05-051-2/+1
| | | | | | | | | | | Currently nine_convert_blend_state has no way of knowing the number of rts. For now set to an upper bound. Signed-off-by: Axel Davy <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4891>
* radeonsi: enable TC-compatible HTILE on demand for best Z/S performanceMarek Olšák2020-05-055-4/+57
| | | | | | | I haven't measured this, but it can only help. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4866>
* radeonsi: allow tc_compatible_htile to be mutableMarek Olšák2020-05-051-44/+56
| | | | | | | | | Move the relevant code from si_init_depth_surface to si_emit_framebuffer_state, so that it can be changed after a pipe_surface is initialized. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4866>
* radeonsi/gfx9: always use IMG_DATA_FORMAT_S8_32 for 8-bit stencilMarek Olšák2020-05-051-2/+1
| | | | | | | | I wanna remove dependency on tc_compatible_htile from non-dynamic states. This should be the same as 8_UINT if HTILE is disabled. Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4866>
* ac/surface: unset RADEON_SURF_TC_COMPATIBLE_HTILE if HTILE hasn't been computedMarek Olšák2020-05-051-0/+8
| | | | | Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4866>
* radeonsi: don't wait for idle at the end of gfx IBsMarek Olšák2020-05-051-0/+13
| | | | | Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4894>
* ac/nir: export some undef as zeroPierre-Eric Pelloux-Prayer2020-05-053-6/+37
| | | | | | | | | | | | | | | | | | NIR already optimizes undef usage. If undef reaches llvm, it's probably because of a broken shader. In this situation, rather than letting llvm use the undef values to do more optimization and probably produce incorrect results, we replace undef values by 0. "undef" values that are directly used in exports are kept as undef, because this allows llvm to optimize them away. This is only enabled for radeonsi. Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2689 Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
* gallium: add a new cap PIPE_CAP_GLSL_ZERO_INITPierre-Eric Pelloux-Prayer2020-05-056-2/+14
| | | | | | | Allows driver to select a zero init mode between the 3 possible values. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
* mesa: extend GLSLZeroInit semanticsPierre-Eric Pelloux-Prayer2020-05-054-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces a new way to zero-init variables but keep the old one to not break any existing behavior. With this change GLSLZeroInit becomes an integer, with the following possible values: - 0: no 0 init - 1: current behavior - 2: new behavior. Similar to 1, except ir_var_function_out type are 0 initialized but ir_var_shader_out. The rationale behind 2 is: zero initializing ir_var_shader_out can prevent some optimization where out variables are completely eliminated when not written to. On the other hand, zero initializing "ir_var_function_out" has no effect on correct shaders but typically helps shadertoy since the main function is: void mainImage(out vec4 fragColor) { ... } So with this change we're sure that fragColor will always get a value. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
* glsl: add a is_implicit_initializer flagPierre-Eric Pelloux-Prayer2020-05-054-2/+18
| | | | | | | | | | | | | | | Shared globals and glsl_zero_init can cause linker errors if the variable is only initialized in 1 place. This commit adds a flag to variables that have been implicitely initialized to be able in this situation to keep the explicit initialization value. Without this change the global-single-initializer-2-shaders piglit test fails when using glsl_zero_init. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
* glsl: rework zero initializationPierre-Eric Pelloux-Prayer2020-05-053-6/+16
| | | | | | | | | This commit makes zero_init a bitfield of types of variables to zeroinit. This will allow some flexibility that will be used in the next commit. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
* glsl: init gl_FragColor if zero_init=truePierre-Eric Pelloux-Prayer2020-05-051-1/+7
| | | | | | | | This fixes shaders doing "gl_FragColor += ..." and doesn't hurt correct shaders, because the zero init is discarded. Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
* radeonsi: don't print gs_copy_shader stats for shaderdbPierre-Eric Pelloux-Prayer2020-05-051-2/+0
| | | | | | Fixes: dbc86fa3de6 ("radeonsi: dump shader stats when hitting the live cache") Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4607>
* radv: enable shaderInt16 unconditionally with LLVM and only GFX8+ with ACOSamuel Pitoiset2020-05-051-1/+1
| | | | | | | | | | | | | | | | | | | | The Vulkan spec says: "shaderInt16 specifies whether 16-bit integers (signed and unsigned) are supported in shader code. If this feature is not enabled, 16-bit integer types must not be used in shader code." I think it's just safe to enable it because 16-bit integers should be fully supported with LLVM and also with ACO and GFX8+. On GFX8 and earlier generations, throughput of 16-bit int is same as 32-bit but that should't change anything. For GFX6-GFX7 ACO support, we have to implement conversions without SDWA. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4874>
* radeonsi: add workaround for issue 2647Pierre-Eric Pelloux-Prayer2020-05-057-4/+45
| | | | | | | | | | | | | | For unknown reasons pixel shaders in KSP game get executed with infinite interpolation coefficients and this causes an infinite loop in the shader. This commit adds a hacky workaround that kills pixel shaders if invalid interp coeffs are detected and enables it for KSP. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2174 Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2647 Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4700>
* zink: use nir_lower_uniforms_to_uboErik Faye-Lund2020-05-051-83/+1
| | | | | | | | | | Instead of open-coding uniform -> UBO lowering, let's instead use the one that already exists. This should make things a bit simpler going forward. Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4734>
* nir: Always create UBO variable when lowering uniforms to uboLouis-Francis Ratté-Boulianne2020-05-051-2/+27
| | | | | | | | | | | | | | | | | | | Zink needs to know the sizes of UBOs, and for normal UBOs we get this from the nir_var_mem_ubo variables. This allows us to treat all of these the same way. We're about to need the same information for the in-progress D3D12 driver, so let's do this in a central location instead of in the driver. This version is also a bit more careful than the Zink version. In particular, for two reasons: 1. We increase the variable bindings when we adjust the pre-existing UBOs. 2. We increase shader->info.num_ubos when we insert a new UBO variable. Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4734>
* mesa/st: consider NumUniformBlocks instead of num_ubos when bindingErik Faye-Lund2020-05-052-2/+2
| | | | | | | | | This is the number of uniform blocks at linking time, not after finalizing shaders. Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4734>
* compiler/glsl: explicitly store NumUniformBlocksErik Faye-Lund2020-05-054-6/+11
| | | | | | | | | | | It's not great to use shader_info for this information, because it might have gone through lowering of uniforms to UBOs, which can change the number of UBOs. So let's make sure we know the size of the UniformBlocks array from when the shader was linked instead. Reviewed-by: Alyssa Rosenzweig <[email protected]> Reviewed-by: Eric Anholt <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4734>
* glsl: rename has_implicit_uint_to_int_conversion to *_int_to_uint_*Danylo Piliaiev2020-05-053-3/+3
| | | | | | | | | | There is no uint to int implicit conversion in glsl, this is just a typo in the name of this function. The correct one would be: has_implicit_int_to_uint_conversion. Signed-off-by: Danylo Piliaiev <[email protected]> Reviewed-by: Erik Faye-Lund <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4884>
* driconf: add force_integer_tex_nearest optionPierre-Eric Pelloux-Prayer2020-05-056-0/+21
| | | | | | | | | | And enable it for "GRID Autosport" and "DIRT: Showdown" games. CC: 20.1 <[email protected]> Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1258 Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4647>
* mesa: add gl_coontext::ForceIntegerTexNearestPierre-Eric Pelloux-Prayer2020-05-056-19/+52
| | | | | | | | | | | | | Some applications incorrectly use GL_LINEAR* values for integers texture. copyimage.c already implemented a tolerance for such app in prepare_target_err. This commit adds a boolean that will treat GL_LINEAR* filters as GL_NEAREST for integer textures. CC: 20.1 <[email protected]> Reviewed-by: Timothy Arceri <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4647>
* aco: remove unecessary p_split_vector with v2b reg classSamuel Pitoiset2020-05-051-80/+33
| | | | | | | | | Should be fine now that RA take full registers for v2b if it's not an SDWA instruction. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Daniel Schürmann <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4879>
* vulkan: Update Vulkan XML and headers to 1.2.140Joshua Ashton2020-05-054-323/+279
| | | | | | | Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Acked-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
* turnip: Remove RANGE_SIZE usageJoshua Ashton2020-05-052-3/+4
| | | | | | | | | These were removed from the latest Vulkan headers https://github.com/KhronosGroup/Vulkan-Docs/issues/1230 Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
* radv: Remove RANGE_SIZE usageJoshua Ashton2020-05-055-12/+26
| | | | | | | | | | These were removed from the latest Vulkan headers https://github.com/KhronosGroup/Vulkan-Docs/issues/1230 Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
* anv: Remove RANGE_SIZE usageJoshua Ashton2020-05-051-3/+0
| | | | | | | | | These were removed from the latest Vulkan headers https://github.com/KhronosGroup/Vulkan-Docs/issues/1230 Reviewed-by: Eric Engestrom <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4878>
* android: iris: add iris_seqno.{c,h} to Makefile.sourcesMauro Rossi2020-05-041-1/+3
| | | | | | | | | | | | Fixes the following undefined symbol building errors: ld.lld: error: undefined symbol: iris_seqno_init >>> referenced by iris_batch.c:187 (external/mesa/src/gallium/drivers/iris/iris_batch.c:187) >>> iris_batch.o:(iris_init_batch) in archive out/target/product/x86_64/obj/STATIC_LIBRARIES/libmesa_pipe_iris_intermediates/libmesa_pipe_iris.a Fixes: e31b703c ("iris: Place a seqno at the end of every batch") Signed-off-by: Mauro Rossi <[email protected]> Acked-by: Tapani Pälli <[email protected]>
* ac/surface: fix MSAA crash with FORCE_SWIZZLE_MODE on gfx9Marek Olšák2020-05-041-1/+3
| | | | | | | | | | Fixes: 3dc2ccc14c0e035 "ac/surface: replace RADEON_SURF_OPTIMIZE_FOR_SPACE with !FORCE_SWIZZLE_MODE" Closes: #2884 Tested-by: Michel Dänzer <[email protected]> Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4862>
* pan/bit: Add IMATH packing testsAlyssa Rosenzweig2020-05-041-1/+17
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bit: Factor out identity swizzle helperAlyssa Rosenzweig2020-05-041-6/+10
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bit: Use swizzle helper for roundAlyssa Rosenzweig2020-05-041-9/+5
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bit: Remove test namesAlyssa Rosenzweig2020-05-041-84/+19
| | | | | | | We already have the disasm which is authoritative. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bit: Interpret v4i8 opsAlyssa Rosenzweig2020-05-041-1/+10
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bit: Interpret IMATHAlyssa Rosenzweig2020-05-041-2/+13
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bi: Don't schedule <32-bit IMATH to FMAAlyssa Rosenzweig2020-05-041-0/+9
| | | | | | | The ops don't exist. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bi: Add SUB.v2i16/SUB.v4i8 opcodes to disasmAlyssa Rosenzweig2020-05-041-0/+2
| | | | | | | Like their ADD counterparts. Only on ADD. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bi: Pack ADD IADD/ISUB for 8/16/32Alyssa Rosenzweig2020-05-042-0/+35
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bi: Pack FMA IADD/ISUB 32Alyssa Rosenzweig2020-05-042-2/+18
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bi: Use IMATH for nir_op_iaddAlyssa Rosenzweig2020-05-043-1/+26
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* pan/bi: Rename BI_ISUB to BI_IMATHAlyssa Rosenzweig2020-05-046-7/+7
| | | | | | | We'll use this for iadd, etc too which share similar characteristics. Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4890>
* freedreno/ir3: Define the bindful uniform/nonuniform desc modes for cat6 a6xx.Eric Anholt2020-05-044-23/+38
| | | | | | | | | These come from the disasm tests, and fix our disasm of blob's uniform/nonuniform cat6 operands. We also now include human-readable names for all the modes we know about (though bindless gets distinguished by its .baseN, like Connor's original disasm). Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
* freedreno/ir3: Sync some new changes from envytools.Eric Anholt2020-05-0411-49/+107
| | | | | | | | With this I also brought in a few new control flow instruction disasm tests that I'd made back when I wrote the disasm test, but which were too far from correct to include until now. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
* freedreno/ir3: Add some more tests of cat6 disasm.Eric Anholt2020-05-041-0/+24
| | | | | | I put these together from traces I had while trying to do LDC for GL. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4857>
* Revert "ac: reassociate FP expressions for inexact instructions for radeonsi"Marek Olšák2020-05-041-9/+0
| | | | | | | | | | | This reverts commit cf2f3c27533d8721abed4cdd4dfb00d4d53e8a0f. It breaks shadows in Unigine Superposition. Fixes: cf2f3c27533d8721abed4cdd4dfb00d4d53e8a0f Reviewed-by: Pierre-Eric Pelloux-Prayer <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4837>
* pan/bit: Add ICMP testsAlyssa Rosenzweig2020-05-041-0/+23
| | | | | Signed-off-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4883>
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